1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // R600 Tablegen instruction definitions
12 //===----------------------------------------------------------------------===//
14 include "R600Intrinsics.td"
15 include "R600InstrFormats.td"
17 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
18 InstR600 <outs, ins, asm, pattern, NullALU> {
20 let Namespace = "AMDGPU";
23 def MEMxi : Operand<iPTR> {
24 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
25 let PrintMethod = "printMemOperand";
28 def MEMrr : Operand<iPTR> {
29 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
32 // Operands for non-registers
34 class InstFlag<string PM = "printOperand", int Default = 0>
35 : OperandWithDefaultOps <i32, (ops (i32 Default))> {
39 // src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers
40 def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
41 let PrintMethod = "printSel";
43 def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> {
44 let PrintMethod = "printBankSwizzle";
47 def LITERAL : InstFlag<"printLiteral">;
49 def WRITE : InstFlag <"printWrite", 1>;
50 def OMOD : InstFlag <"printOMOD">;
51 def REL : InstFlag <"printRel">;
52 def CLAMP : InstFlag <"printClamp">;
53 def NEG : InstFlag <"printNeg">;
54 def ABS : InstFlag <"printAbs">;
55 def UEM : InstFlag <"printUpdateExecMask">;
56 def UP : InstFlag <"printUpdatePred">;
58 // XXX: The r600g finalizer in Mesa expects last to be one in most cases.
59 // Once we start using the packetizer in this backend we should have this
61 def LAST : InstFlag<"printLast", 1>;
62 def RSel : Operand<i32> {
63 let PrintMethod = "printRSel";
65 def CT: Operand<i32> {
66 let PrintMethod = "printCT";
69 def FRAMEri : Operand<iPTR> {
70 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index);
73 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
74 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
75 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
76 def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>;
77 def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;
78 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
81 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
85 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
87 // Class for instructions with only one source register.
88 // If you add new ins to this instruction, make sure they are listed before
89 // $literal, because the backend currently assumes that the last operand is
90 // a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in
91 // R600Defines.h, R600InstrInfo::buildDefaultInstruction(),
92 // and R600InstrInfo::getOperandIdx().
93 class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
94 InstrItinClass itin = AnyALU> :
95 InstR600 <(outs R600_Reg32:$dst),
96 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
97 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
98 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
99 BANK_SWIZZLE:$bank_swizzle),
100 !strconcat(" ", opName,
101 "$clamp $last $dst$write$dst_rel$omod, "
102 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
103 "$pred_sel $bank_swizzle"),
107 R600ALU_Word1_OP2 <inst> {
113 let update_exec_mask = 0;
115 let HasNativeOperands = 1;
118 let DisableEncoding = "$literal";
119 let UseNamedOperandTable = 1;
121 let Inst{31-0} = Word0;
122 let Inst{63-32} = Word1;
125 class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
126 InstrItinClass itin = AnyALU> :
127 R600_1OP <inst, opName,
128 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))]
131 // If you add or change the operands for R600_2OP instructions, you must
132 // also update the R600Op2OperandIndex::ROI enum in R600Defines.h,
133 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
134 class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
135 InstrItinClass itin = AnyALU> :
136 InstR600 <(outs R600_Reg32:$dst),
137 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
138 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
139 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
140 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
141 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
142 BANK_SWIZZLE:$bank_swizzle),
143 !strconcat(" ", opName,
144 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
145 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
146 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
147 "$pred_sel $bank_swizzle"),
151 R600ALU_Word1_OP2 <inst> {
153 let HasNativeOperands = 1;
156 let DisableEncoding = "$literal";
157 let UseNamedOperandTable = 1;
159 let Inst{31-0} = Word0;
160 let Inst{63-32} = Word1;
163 class R600_2OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
164 InstrItinClass itim = AnyALU> :
165 R600_2OP <inst, opName,
166 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
170 // If you add our change the operands for R600_3OP instructions, you must
171 // also update the R600Op3OperandIndex::ROI enum in R600Defines.h,
172 // R600InstrInfo::buildDefaultInstruction(), and
173 // R600InstrInfo::getOperandIdx().
174 class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
175 InstrItinClass itin = AnyALU> :
176 InstR600 <(outs R600_Reg32:$dst),
177 (ins REL:$dst_rel, CLAMP:$clamp,
178 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
179 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
180 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
181 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
182 BANK_SWIZZLE:$bank_swizzle),
183 !strconcat(" ", opName, "$clamp $last $dst$dst_rel, "
184 "$src0_neg$src0$src0_rel, "
185 "$src1_neg$src1$src1_rel, "
186 "$src2_neg$src2$src2_rel, "
192 R600ALU_Word1_OP3<inst>{
194 let HasNativeOperands = 1;
195 let DisableEncoding = "$literal";
197 let UseNamedOperandTable = 1;
200 let Inst{31-0} = Word0;
201 let Inst{63-32} = Word1;
204 class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern,
205 InstrItinClass itin = VecALU> :
206 InstR600 <(outs R600_Reg32:$dst),
214 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
216 def TEX_SHADOW : PatLeaf<
218 [{uint32_t TType = (uint32_t)N->getZExtValue();
219 return (TType >= 6 && TType <= 8) || (TType >= 11 && TType <= 13);
223 def TEX_RECT : PatLeaf<
225 [{uint32_t TType = (uint32_t)N->getZExtValue();
230 def TEX_ARRAY : PatLeaf<
232 [{uint32_t TType = (uint32_t)N->getZExtValue();
233 return TType == 9 || TType == 10 || TType == 16;
237 def TEX_SHADOW_ARRAY : PatLeaf<
239 [{uint32_t TType = (uint32_t)N->getZExtValue();
240 return TType == 11 || TType == 12 || TType == 17;
244 def TEX_MSAA : PatLeaf<
246 [{uint32_t TType = (uint32_t)N->getZExtValue();
251 def TEX_ARRAY_MSAA : PatLeaf<
253 [{uint32_t TType = (uint32_t)N->getZExtValue();
258 class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> mask, dag outs,
259 dag ins, string asm, list<dag> pattern> :
260 InstR600ISA <outs, ins, asm, pattern>,
261 CF_ALLOC_EXPORT_WORD0_RAT, CF_ALLOC_EXPORT_WORD1_BUF {
264 let rat_inst = ratinst;
266 // XXX: Have a separate instruction for non-indexed writes.
272 let comp_mask = mask;
275 let cf_inst = cfinst;
279 let Inst{31-0} = Word0;
280 let Inst{63-32} = Word1;
284 class VTX_READ <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
285 : InstR600ISA <outs, (ins MEMxi:$src_gpr), name, pattern>,
290 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
291 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
292 // however, based on my testing if USE_CONST_FIELDS is set, then all
293 // these fields need to be set to 0.
294 let USE_CONST_FIELDS = 0;
295 let NUM_FORMAT_ALL = 1;
296 let FORMAT_COMP_ALL = 0;
297 let SRF_MODE_ALL = 0;
299 let Inst{63-32} = Word1;
300 // LLVM can only encode 64-bit instructions, so these fields are manually
301 // encoded in R600CodeEmitter
304 // bits<2> ENDIAN_SWAP = 0;
305 // bits<1> CONST_BUF_NO_STRIDE = 0;
306 // bits<1> MEGA_FETCH = 0;
307 // bits<1> ALT_CONST = 0;
308 // bits<2> BUFFER_INDEX_MODE = 0;
310 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
311 // is done in R600CodeEmitter
313 // Inst{79-64} = OFFSET;
314 // Inst{81-80} = ENDIAN_SWAP;
315 // Inst{82} = CONST_BUF_NO_STRIDE;
316 // Inst{83} = MEGA_FETCH;
317 // Inst{84} = ALT_CONST;
318 // Inst{86-85} = BUFFER_INDEX_MODE;
319 // Inst{95-86} = 0; Reserved
321 // VTX_WORD3 (Padding)
328 class LoadParamFrag <PatFrag load_type> : PatFrag <
329 (ops node:$ptr), (load_type node:$ptr),
330 [{ return isConstantLoad(dyn_cast<LoadSDNode>(N), 0); }]
333 def load_param : LoadParamFrag<load>;
334 def load_param_exti8 : LoadParamFrag<az_extloadi8>;
335 def load_param_exti16 : LoadParamFrag<az_extloadi16>;
337 def isR600 : Predicate<"Subtarget.getGeneration() <= AMDGPUSubtarget::R700">;
338 def isR700 : Predicate<"Subtarget.getGeneration() == AMDGPUSubtarget::R700">;
339 def isEG : Predicate<
340 "Subtarget.getGeneration() >= AMDGPUSubtarget::EVERGREEN && "
341 "Subtarget.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && "
342 "!Subtarget.hasCaymanISA()">;
344 def isCayman : Predicate<"Subtarget.hasCaymanISA()">;
345 def isEGorCayman : Predicate<"Subtarget.getGeneration() == "
346 "AMDGPUSubtarget::EVERGREEN"
347 "|| Subtarget.getGeneration() =="
348 "AMDGPUSubtarget::NORTHERN_ISLANDS">;
350 def isR600toCayman : Predicate<
351 "Subtarget.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">;
353 //===----------------------------------------------------------------------===//
355 //===----------------------------------------------------------------------===//
357 def INTERP_PAIR_XY : AMDGPUShaderInst <
358 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1),
359 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
360 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
363 def INTERP_PAIR_ZW : AMDGPUShaderInst <
364 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1),
365 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
366 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
369 def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS",
370 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>,
374 def DOT4 : SDNode<"AMDGPUISD::DOT4",
375 SDTypeProfile<1, 8, [SDTCisFP<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32>,
376 SDTCisVT<3, f32>, SDTCisVT<4, f32>, SDTCisVT<5, f32>,
377 SDTCisVT<6, f32>, SDTCisVT<7, f32>, SDTCisVT<8, f32>]>,
381 def COS_HW : SDNode<"AMDGPUISD::COS_HW",
382 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>
385 def SIN_HW : SDNode<"AMDGPUISD::SIN_HW",
386 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>
389 def TEXTURE_FETCH_Type : SDTypeProfile<1, 19, [SDTCisFP<0>]>;
391 def TEXTURE_FETCH: SDNode<"AMDGPUISD::TEXTURE_FETCH", TEXTURE_FETCH_Type, []>;
393 multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> {
394 def : Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR,
395 (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw),
396 (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz),
397 (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z),
398 (i32 imm:$DST_SEL_W),
399 (i32 imm:$RESOURCE_ID), (i32 imm:$SAMPLER_ID),
400 (i32 imm:$COORD_TYPE_X), (i32 imm:$COORD_TYPE_Y), (i32 imm:$COORD_TYPE_Z),
401 (i32 imm:$COORD_TYPE_W)),
402 (inst R600_Reg128:$SRC_GPR,
403 imm:$srcx, imm:$srcy, imm:$srcz, imm:$srcw,
404 imm:$offsetx, imm:$offsety, imm:$offsetz,
405 imm:$DST_SEL_X, imm:$DST_SEL_Y, imm:$DST_SEL_Z,
407 imm:$RESOURCE_ID, imm:$SAMPLER_ID,
408 imm:$COORD_TYPE_X, imm:$COORD_TYPE_Y, imm:$COORD_TYPE_Z,
412 //===----------------------------------------------------------------------===//
413 // Interpolation Instructions
414 //===----------------------------------------------------------------------===//
416 def INTERP_VEC_LOAD : AMDGPUShaderInst <
417 (outs R600_Reg128:$dst),
419 "INTERP_LOAD $src0 : $dst",
422 def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> {
423 let bank_swizzle = 5;
426 def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> {
427 let bank_swizzle = 5;
430 def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
432 //===----------------------------------------------------------------------===//
433 // Export Instructions
434 //===----------------------------------------------------------------------===//
436 def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
438 def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType,
439 [SDNPHasChain, SDNPSideEffect]>;
442 field bits<32> Word0;
449 let Word0{12-0} = arraybase;
450 let Word0{14-13} = type;
451 let Word0{21-15} = gpr;
452 let Word0{22} = 0; // RW_REL
453 let Word0{29-23} = 0; // INDEX_GPR
454 let Word0{31-30} = elem_size;
457 class ExportSwzWord1 {
458 field bits<32> Word1;
467 let Word1{2-0} = sw_x;
468 let Word1{5-3} = sw_y;
469 let Word1{8-6} = sw_z;
470 let Word1{11-9} = sw_w;
473 class ExportBufWord1 {
474 field bits<32> Word1;
481 let Word1{11-0} = arraySize;
482 let Word1{15-12} = compMask;
485 multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
486 def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg),
488 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
489 0, 61, 0, 7, 7, 7, cf_inst, 0)
492 def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg),
494 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
495 0, 61, 7, 0, 7, 7, cf_inst, 0)
498 def : Pat<(int_R600_store_dummy (i32 imm:$type)),
500 (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0)
503 def : Pat<(int_R600_store_dummy 1),
505 (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
508 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
509 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),
510 (ExportInst R600_Reg128:$src, imm:$type, imm:$base,
511 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0)
516 multiclass SteamOutputExportPattern<Instruction ExportInst,
517 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {
519 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
520 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)),
521 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
522 4095, imm:$mask, buf0inst, 0)>;
524 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
525 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)),
526 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
527 4095, imm:$mask, buf1inst, 0)>;
529 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
530 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)),
531 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
532 4095, imm:$mask, buf2inst, 0)>;
534 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
535 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)),
536 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
537 4095, imm:$mask, buf3inst, 0)>;
540 // Export Instructions should not be duplicated by TailDuplication pass
541 // (which assumes that duplicable instruction are affected by exec mask)
542 let usesCustomInserter = 1, isNotDuplicable = 1 in {
544 class ExportSwzInst : InstR600ISA<(
546 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
547 RSel:$sw_x, RSel:$sw_y, RSel:$sw_z, RSel:$sw_w, i32imm:$inst,
549 !strconcat("EXPORT", " $gpr.$sw_x$sw_y$sw_z$sw_w"),
550 []>, ExportWord0, ExportSwzWord1 {
552 let Inst{31-0} = Word0;
553 let Inst{63-32} = Word1;
556 } // End usesCustomInserter = 1
558 class ExportBufInst : InstR600ISA<(
560 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
561 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop),
562 !strconcat("EXPORT", " $gpr"),
563 []>, ExportWord0, ExportBufWord1 {
565 let Inst{31-0} = Word0;
566 let Inst{63-32} = Word1;
569 //===----------------------------------------------------------------------===//
570 // Control Flow Instructions
571 //===----------------------------------------------------------------------===//
574 def KCACHE : InstFlag<"printKCache">;
576 class ALU_CLAUSE<bits<4> inst, string OpName> : AMDGPUInst <(outs),
577 (ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1,
578 KCACHE:$KCACHE_MODE0, KCACHE:$KCACHE_MODE1,
579 i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1,
580 i32imm:$COUNT, i32imm:$Enabled),
581 !strconcat(OpName, " $COUNT, @$ADDR, "
582 "KC0[$KCACHE_MODE0], KC1[$KCACHE_MODE1]"),
583 [] >, CF_ALU_WORD0, CF_ALU_WORD1 {
588 let WHOLE_QUAD_MODE = 0;
591 let Inst{31-0} = Word0;
592 let Inst{63-32} = Word1;
595 class CF_WORD0_R600 {
596 field bits<32> Word0;
603 class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
604 ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 {
611 let VALID_PIXEL_MODE = 0;
613 let COUNT = CNT{2-0};
615 let COUNT_3 = CNT{3};
616 let END_OF_PROGRAM = 0;
617 let WHOLE_QUAD_MODE = 0;
619 let Inst{31-0} = Word0;
620 let Inst{63-32} = Word1;
623 class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
624 ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG {
629 let JUMPTABLE_SEL = 0;
631 let VALID_PIXEL_MODE = 0;
633 let END_OF_PROGRAM = 0;
635 let Inst{31-0} = Word0;
636 let Inst{63-32} = Word1;
639 def CF_ALU : ALU_CLAUSE<8, "ALU">;
640 def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">;
641 def CF_ALU_POP_AFTER : ALU_CLAUSE<10, "ALU_POP_AFTER">;
643 def FETCH_CLAUSE : AMDGPUInst <(outs),
644 (ins i32imm:$addr), "Fetch clause starting at $addr:", [] > {
650 def ALU_CLAUSE : AMDGPUInst <(outs),
651 (ins i32imm:$addr), "ALU clause starting at $addr:", [] > {
657 def LITERALS : AMDGPUInst <(outs),
658 (ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > {
663 let Inst{31-0} = literal1;
664 let Inst{63-32} = literal2;
667 def PAD : AMDGPUInst <(outs), (ins), "PAD", [] > {
671 let Predicates = [isR600toCayman] in {
673 //===----------------------------------------------------------------------===//
674 // Common Instructions R600, R700, Evergreen, Cayman
675 //===----------------------------------------------------------------------===//
677 def ADD : R600_2OP_Helper <0x0, "ADD", fadd>;
678 // Non-IEEE MUL: 0 * anything = 0
679 def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", int_AMDGPU_mul>;
680 def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;
681 def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax>;
682 def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin>;
684 // For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
685 // so some of the instruction names don't match the asm string.
686 // XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
687 def SETE : R600_2OP <
689 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_EQ))]
694 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_GT))]
699 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_GE))]
704 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_NE))]
707 def SETE_DX10 : R600_2OP <
709 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_EQ))]
712 def SETGT_DX10 : R600_2OP <
714 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_GT))]
717 def SETGE_DX10 : R600_2OP <
719 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_GE))]
722 def SETNE_DX10 : R600_2OP <
724 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_NE))]
727 def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;
728 def TRUNC : R600_1OP_Helper <0x11, "TRUNC", int_AMDGPU_trunc>;
729 def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
730 def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
731 def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
733 def MOV : R600_1OP <0x19, "MOV", []>;
735 let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {
737 class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst <
738 (outs R600_Reg32:$dst),
744 } // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1
746 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
749 (MOV_IMM_I32 imm:$val)
752 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
755 (MOV_IMM_F32 fpimm:$val)
758 def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>;
759 def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>;
760 def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>;
761 def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>;
763 let hasSideEffects = 1 in {
765 def KILLGT : R600_2OP <0x2D, "KILLGT", []>;
767 } // end hasSideEffects
769 def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;
770 def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>;
771 def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>;
772 def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>;
773 def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>;
774 def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>;
775 def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", AMDGPUsmax>;
776 def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", AMDGPUsmin>;
777 def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", AMDGPUumax>;
778 def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", AMDGPUumin>;
780 def SETE_INT : R600_2OP <
782 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETEQ))]
785 def SETGT_INT : R600_2OP <
787 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))]
790 def SETGE_INT : R600_2OP <
792 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))]
795 def SETNE_INT : R600_2OP <
797 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETNE))]
800 def SETGT_UINT : R600_2OP <
802 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))]
805 def SETGE_UINT : R600_2OP <
807 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGE))]
810 def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>;
811 def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>;
812 def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>;
813 def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>;
815 def CNDE_INT : R600_3OP <
817 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_EQ))]
820 def CNDGE_INT : R600_3OP <
822 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_GE))]
825 def CNDGT_INT : R600_3OP <
827 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_GT))]
830 //===----------------------------------------------------------------------===//
831 // Texture instructions
832 //===----------------------------------------------------------------------===//
834 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
836 class R600_TEX <bits<11> inst, string opName> :
837 InstR600 <(outs R600_Reg128:$DST_GPR),
838 (ins R600_Reg128:$SRC_GPR,
839 RSel:$srcx, RSel:$srcy, RSel:$srcz, RSel:$srcw,
840 i32imm:$offsetx, i32imm:$offsety, i32imm:$offsetz,
841 RSel:$DST_SEL_X, RSel:$DST_SEL_Y, RSel:$DST_SEL_Z, RSel:$DST_SEL_W,
842 i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID,
843 CT:$COORD_TYPE_X, CT:$COORD_TYPE_Y, CT:$COORD_TYPE_Z,
846 " $DST_GPR.$DST_SEL_X$DST_SEL_Y$DST_SEL_Z$DST_SEL_W, "
847 "$SRC_GPR.$srcx$srcy$srcz$srcw "
848 "RID:$RESOURCE_ID SID:$SAMPLER_ID "
849 "CT:$COORD_TYPE_X$COORD_TYPE_Y$COORD_TYPE_Z$COORD_TYPE_W"),
851 NullALU>, TEX_WORD0, TEX_WORD1, TEX_WORD2 {
852 let Inst{31-0} = Word0;
853 let Inst{63-32} = Word1;
855 let TEX_INST = inst{4-0};
861 let FETCH_WHOLE_QUAD = 0;
863 let SAMPLER_INDEX_MODE = 0;
864 let RESOURCE_INDEX_MODE = 0;
869 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
873 def TEX_SAMPLE : R600_TEX <0x10, "TEX_SAMPLE">;
874 def TEX_SAMPLE_C : R600_TEX <0x18, "TEX_SAMPLE_C">;
875 def TEX_SAMPLE_L : R600_TEX <0x11, "TEX_SAMPLE_L">;
876 def TEX_SAMPLE_C_L : R600_TEX <0x19, "TEX_SAMPLE_C_L">;
877 def TEX_SAMPLE_LB : R600_TEX <0x12, "TEX_SAMPLE_LB">;
878 def TEX_SAMPLE_C_LB : R600_TEX <0x1A, "TEX_SAMPLE_C_LB">;
879 def TEX_LD : R600_TEX <0x03, "TEX_LD">;
880 def TEX_GET_TEXTURE_RESINFO : R600_TEX <0x04, "TEX_GET_TEXTURE_RESINFO">;
881 def TEX_GET_GRADIENTS_H : R600_TEX <0x07, "TEX_GET_GRADIENTS_H">;
882 def TEX_GET_GRADIENTS_V : R600_TEX <0x08, "TEX_GET_GRADIENTS_V">;
883 def TEX_SET_GRADIENTS_H : R600_TEX <0x0B, "TEX_SET_GRADIENTS_H">;
884 def TEX_SET_GRADIENTS_V : R600_TEX <0x0C, "TEX_SET_GRADIENTS_V">;
885 def TEX_SAMPLE_G : R600_TEX <0x14, "TEX_SAMPLE_G">;
886 def TEX_SAMPLE_C_G : R600_TEX <0x1C, "TEX_SAMPLE_C_G">;
888 defm : TexPattern<0, TEX_SAMPLE>;
889 defm : TexPattern<1, TEX_SAMPLE_C>;
890 defm : TexPattern<2, TEX_SAMPLE_L>;
891 defm : TexPattern<3, TEX_SAMPLE_C_L>;
892 defm : TexPattern<4, TEX_SAMPLE_LB>;
893 defm : TexPattern<5, TEX_SAMPLE_C_LB>;
894 defm : TexPattern<6, TEX_LD, v4i32>;
895 defm : TexPattern<7, TEX_GET_TEXTURE_RESINFO, v4i32>;
896 defm : TexPattern<8, TEX_GET_GRADIENTS_H>;
897 defm : TexPattern<9, TEX_GET_GRADIENTS_V>;
899 //===----------------------------------------------------------------------===//
900 // Helper classes for common instructions
901 //===----------------------------------------------------------------------===//
903 class MUL_LIT_Common <bits<5> inst> : R600_3OP <
908 class MULADD_Common <bits<5> inst> : R600_3OP <
913 class MULADD_IEEE_Common <bits<5> inst> : R600_3OP <
915 [(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))]
918 class CNDE_Common <bits<5> inst> : R600_3OP <
920 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_EQ))]
923 class CNDGT_Common <bits<5> inst> : R600_3OP <
925 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_GT))]
928 class CNDGE_Common <bits<5> inst> : R600_3OP <
930 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_GE))]
934 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
935 class R600_VEC2OP<list<dag> pattern> : InstR600 <(outs R600_Reg32:$dst), (ins
937 UEM:$update_exec_mask_X, UP:$update_pred_X, WRITE:$write_X,
938 OMOD:$omod_X, REL:$dst_rel_X, CLAMP:$clamp_X,
939 R600_TReg32_X:$src0_X, NEG:$src0_neg_X, REL:$src0_rel_X, ABS:$src0_abs_X, SEL:$src0_sel_X,
940 R600_TReg32_X:$src1_X, NEG:$src1_neg_X, REL:$src1_rel_X, ABS:$src1_abs_X, SEL:$src1_sel_X,
941 R600_Pred:$pred_sel_X,
943 UEM:$update_exec_mask_Y, UP:$update_pred_Y, WRITE:$write_Y,
944 OMOD:$omod_Y, REL:$dst_rel_Y, CLAMP:$clamp_Y,
945 R600_TReg32_Y:$src0_Y, NEG:$src0_neg_Y, REL:$src0_rel_Y, ABS:$src0_abs_Y, SEL:$src0_sel_Y,
946 R600_TReg32_Y:$src1_Y, NEG:$src1_neg_Y, REL:$src1_rel_Y, ABS:$src1_abs_Y, SEL:$src1_sel_Y,
947 R600_Pred:$pred_sel_Y,
949 UEM:$update_exec_mask_Z, UP:$update_pred_Z, WRITE:$write_Z,
950 OMOD:$omod_Z, REL:$dst_rel_Z, CLAMP:$clamp_Z,
951 R600_TReg32_Z:$src0_Z, NEG:$src0_neg_Z, REL:$src0_rel_Z, ABS:$src0_abs_Z, SEL:$src0_sel_Z,
952 R600_TReg32_Z:$src1_Z, NEG:$src1_neg_Z, REL:$src1_rel_Z, ABS:$src1_abs_Z, SEL:$src1_sel_Z,
953 R600_Pred:$pred_sel_Z,
955 UEM:$update_exec_mask_W, UP:$update_pred_W, WRITE:$write_W,
956 OMOD:$omod_W, REL:$dst_rel_W, CLAMP:$clamp_W,
957 R600_TReg32_W:$src0_W, NEG:$src0_neg_W, REL:$src0_rel_W, ABS:$src0_abs_W, SEL:$src0_sel_W,
958 R600_TReg32_W:$src1_W, NEG:$src1_neg_W, REL:$src1_rel_W, ABS:$src1_abs_W, SEL:$src1_sel_W,
959 R600_Pred:$pred_sel_W,
960 LITERAL:$literal0, LITERAL:$literal1),
965 let UseNamedOperandTable = 1;
970 def DOT_4 : R600_VEC2OP<[(set R600_Reg32:$dst, (DOT4
971 R600_TReg32_X:$src0_X, R600_TReg32_X:$src1_X,
972 R600_TReg32_Y:$src0_Y, R600_TReg32_Y:$src1_Y,
973 R600_TReg32_Z:$src0_Z, R600_TReg32_Z:$src1_Z,
974 R600_TReg32_W:$src0_W, R600_TReg32_W:$src1_W))]>;
977 class DOT4_Common <bits<11> inst> : R600_2OP <inst, "DOT4", []>;
980 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
981 multiclass CUBE_Common <bits<11> inst> {
983 def _pseudo : InstR600 <
984 (outs R600_Reg128:$dst),
985 (ins R600_Reg128:$src0),
987 [(set v4f32:$dst, (int_AMDGPU_cube v4f32:$src0))],
991 let UseNamedOperandTable = 1;
994 def _real : R600_2OP <inst, "CUBE", []>;
996 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
998 class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
999 inst, "EXP_IEEE", fexp2
1002 let Itinerary = TransALU;
1005 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper <
1006 inst, "FLT_TO_INT", fp_to_sint
1009 let Itinerary = TransALU;
1012 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1013 inst, "INT_TO_FLT", sint_to_fp
1016 let Itinerary = TransALU;
1019 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1020 inst, "FLT_TO_UINT", fp_to_uint
1023 let Itinerary = TransALU;
1026 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1027 inst, "UINT_TO_FLT", uint_to_fp
1030 let Itinerary = TransALU;
1033 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
1034 inst, "LOG_CLAMPED", []
1037 class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1038 inst, "LOG_IEEE", flog2
1041 let Itinerary = TransALU;
1044 class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>;
1045 class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>;
1046 class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>;
1047 class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper <
1048 inst, "MULHI_INT", mulhs
1051 let Itinerary = TransALU;
1053 class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper <
1054 inst, "MULHI", mulhu
1057 let Itinerary = TransALU;
1059 class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper <
1060 inst, "MULLO_INT", mul
1063 let Itinerary = TransALU;
1065 class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []> {
1067 let Itinerary = TransALU;
1070 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
1071 inst, "RECIP_CLAMPED", []
1074 let Itinerary = TransALU;
1077 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
1078 inst, "RECIP_IEEE", [(set f32:$dst, (fdiv FP_ONE, f32:$src0))]
1081 let Itinerary = TransALU;
1084 class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1085 inst, "RECIP_UINT", AMDGPUurecip
1088 let Itinerary = TransALU;
1091 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper <
1092 inst, "RECIPSQRT_CLAMPED", int_AMDGPU_rsq
1095 let Itinerary = TransALU;
1098 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP <
1099 inst, "RECIPSQRT_IEEE", []
1102 let Itinerary = TransALU;
1105 class SIN_Common <bits<11> inst> : R600_1OP <
1106 inst, "SIN", [(set f32:$dst, (SIN_HW f32:$src0))]>{
1109 let Itinerary = TransALU;
1112 class COS_Common <bits<11> inst> : R600_1OP <
1113 inst, "COS", [(set f32:$dst, (COS_HW f32:$src0))]> {
1116 let Itinerary = TransALU;
1119 //===----------------------------------------------------------------------===//
1120 // Helper patterns for complex intrinsics
1121 //===----------------------------------------------------------------------===//
1123 multiclass DIV_Common <InstR600 recip_ieee> {
1125 (int_AMDGPU_div f32:$src0, f32:$src1),
1126 (MUL_IEEE $src0, (recip_ieee $src1))
1130 (fdiv f32:$src0, f32:$src1),
1131 (MUL_IEEE $src0, (recip_ieee $src1))
1135 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee>
1137 (int_TGSI_lit_z f32:$src_x, f32:$src_y, f32:$src_w),
1138 (exp_ieee (mul_lit (log_clamped (MAX $src_y, (f32 ZERO))), $src_w, $src_x))
1141 //===----------------------------------------------------------------------===//
1142 // R600 / R700 Instructions
1143 //===----------------------------------------------------------------------===//
1145 let Predicates = [isR600] in {
1147 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
1148 def MULADD_r600 : MULADD_Common<0x10>;
1149 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>;
1150 def CNDE_r600 : CNDE_Common<0x18>;
1151 def CNDGT_r600 : CNDGT_Common<0x19>;
1152 def CNDGE_r600 : CNDGE_Common<0x1A>;
1153 def DOT4_r600 : DOT4_Common<0x50>;
1154 defm CUBE_r600 : CUBE_Common<0x52>;
1155 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
1156 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
1157 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
1158 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
1159 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
1160 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
1161 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
1162 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
1163 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
1164 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
1165 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
1166 def SIN_r600 : SIN_Common<0x6E>;
1167 def COS_r600 : COS_Common<0x6F>;
1168 def ASHR_r600 : ASHR_Common<0x70>;
1169 def LSHR_r600 : LSHR_Common<0x71>;
1170 def LSHL_r600 : LSHL_Common<0x72>;
1171 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
1172 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
1173 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
1174 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
1175 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
1177 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
1178 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>;
1179 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
1181 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>;
1183 def R600_ExportSwz : ExportSwzInst {
1184 let Word1{20-17} = 0; // BURST_COUNT
1185 let Word1{21} = eop;
1186 let Word1{22} = 1; // VALID_PIXEL_MODE
1187 let Word1{30-23} = inst;
1188 let Word1{31} = 1; // BARRIER
1190 defm : ExportPattern<R600_ExportSwz, 39>;
1192 def R600_ExportBuf : ExportBufInst {
1193 let Word1{20-17} = 0; // BURST_COUNT
1194 let Word1{21} = eop;
1195 let Word1{22} = 1; // VALID_PIXEL_MODE
1196 let Word1{30-23} = inst;
1197 let Word1{31} = 1; // BARRIER
1199 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>;
1201 def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$CNT),
1202 "TEX $CNT @$ADDR"> {
1205 def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$CNT),
1206 "VTX $CNT @$ADDR"> {
1209 def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR),
1210 "LOOP_START_DX10 @$ADDR"> {
1214 def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1218 def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR),
1219 "LOOP_BREAK @$ADDR"> {
1223 def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR),
1224 "CONTINUE @$ADDR"> {
1228 def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1229 "JUMP @$ADDR POP:$POP_COUNT"> {
1232 def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1233 "ELSE @$ADDR POP:$POP_COUNT"> {
1236 def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> {
1241 def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1242 "POP @$ADDR POP:$POP_COUNT"> {
1245 def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> {
1249 let END_OF_PROGRAM = 1;
1254 //===----------------------------------------------------------------------===//
1255 // R700 Only instructions
1256 //===----------------------------------------------------------------------===//
1258 let Predicates = [isR700] in {
1259 def SIN_r700 : SIN_Common<0x6E>;
1260 def COS_r700 : COS_Common<0x6F>;
1263 //===----------------------------------------------------------------------===//
1264 // Evergreen Only instructions
1265 //===----------------------------------------------------------------------===//
1267 let Predicates = [isEG] in {
1269 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
1270 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
1272 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
1273 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
1274 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
1275 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
1276 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
1277 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
1278 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
1279 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
1280 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
1281 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
1282 def SIN_eg : SIN_Common<0x8D>;
1283 def COS_eg : COS_Common<0x8E>;
1285 def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>;
1286 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>;
1288 //===----------------------------------------------------------------------===//
1289 // Memory read/write instructions
1290 //===----------------------------------------------------------------------===//
1291 let usesCustomInserter = 1 in {
1293 class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> mask, string name,
1295 : EG_CF_RAT <0x57, 0x2, mask, (outs), ins, name, pattern> {
1298 } // End usesCustomInserter = 1
1301 def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg <
1302 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1303 0x1, "RAT_WRITE_CACHELESS_32_eg $rw_gpr, $index_gpr, $eop",
1304 [(global_store i32:$rw_gpr, i32:$index_gpr)]
1308 def RAT_WRITE_CACHELESS_64_eg : RAT_WRITE_CACHELESS_eg <
1309 (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1310 0x3, "RAT_WRITE_CACHELESS_64_eg $rw_gpr.XY, $index_gpr, $eop",
1311 [(global_store v2i32:$rw_gpr, i32:$index_gpr)]
1315 def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
1316 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1317 0xf, "RAT_WRITE_CACHELESS_128 $rw_gpr.XYZW, $index_gpr, $eop",
1318 [(global_store v4i32:$rw_gpr, i32:$index_gpr)]
1321 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
1322 : VTX_WORD0_eg, VTX_READ<name, buffer_id, outs, pattern> {
1327 let FETCH_WHOLE_QUAD = 0;
1328 let BUFFER_ID = buffer_id;
1330 // XXX: We can infer this field based on the SRC_GPR. This would allow us
1331 // to store vertex addresses in any channel, not just X.
1334 let Inst{31-0} = Word0;
1337 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
1338 : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id,
1339 (outs R600_TReg32_X:$dst_gpr), pattern> {
1341 let MEGA_FETCH_COUNT = 1;
1343 let DST_SEL_Y = 7; // Masked
1344 let DST_SEL_Z = 7; // Masked
1345 let DST_SEL_W = 7; // Masked
1346 let DATA_FORMAT = 1; // FMT_8
1349 class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
1350 : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id,
1351 (outs R600_TReg32_X:$dst_gpr), pattern> {
1352 let MEGA_FETCH_COUNT = 2;
1354 let DST_SEL_Y = 7; // Masked
1355 let DST_SEL_Z = 7; // Masked
1356 let DST_SEL_W = 7; // Masked
1357 let DATA_FORMAT = 5; // FMT_16
1361 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
1362 : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id,
1363 (outs R600_TReg32_X:$dst_gpr), pattern> {
1365 let MEGA_FETCH_COUNT = 4;
1367 let DST_SEL_Y = 7; // Masked
1368 let DST_SEL_Z = 7; // Masked
1369 let DST_SEL_W = 7; // Masked
1370 let DATA_FORMAT = 0xD; // COLOR_32
1372 // This is not really necessary, but there were some GPU hangs that appeared
1373 // to be caused by ALU instructions in the next instruction group that wrote
1374 // to the $src_gpr registers of the VTX_READ.
1376 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
1377 // %T2_X<def> = MOV %ZERO
1378 //Adding this constraint prevents this from happening.
1379 let Constraints = "$src_gpr.ptr = $dst_gpr";
1382 class VTX_READ_64_eg <bits<8> buffer_id, list<dag> pattern>
1383 : VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr", buffer_id,
1384 (outs R600_Reg64:$dst_gpr), pattern> {
1386 let MEGA_FETCH_COUNT = 8;
1391 let DATA_FORMAT = 0x1D; // COLOR_32_32
1394 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
1395 : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id,
1396 (outs R600_Reg128:$dst_gpr), pattern> {
1398 let MEGA_FETCH_COUNT = 16;
1403 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
1405 // XXX: Need to force VTX_READ_128 instructions to write to the same register
1406 // that holds its buffer address to avoid potential hangs. We can't use
1407 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
1408 // registers are different sizes.
1411 //===----------------------------------------------------------------------===//
1412 // VTX Read from parameter memory space
1413 //===----------------------------------------------------------------------===//
1415 def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0,
1416 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))]
1419 def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0,
1420 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))]
1423 def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0,
1424 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1427 def VTX_READ_PARAM_64_eg : VTX_READ_64_eg <0,
1428 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1431 def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0,
1432 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1435 //===----------------------------------------------------------------------===//
1436 // VTX Read from global memory space
1437 //===----------------------------------------------------------------------===//
1440 def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1,
1441 [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))]
1444 def VTX_READ_GLOBAL_16_eg : VTX_READ_16_eg <1,
1445 [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))]
1449 def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1,
1450 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1454 def VTX_READ_GLOBAL_64_eg : VTX_READ_64_eg <1,
1455 [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1459 def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
1460 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1463 } // End Predicates = [isEG]
1465 //===----------------------------------------------------------------------===//
1466 // Evergreen / Cayman Instructions
1467 //===----------------------------------------------------------------------===//
1469 let Predicates = [isEGorCayman] in {
1471 // BFE_UINT - bit_extract, an optimization for mask and shift
1476 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
1481 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
1482 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
1483 // (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
1484 // (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
1485 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
1486 [(set i32:$dst, (int_AMDIL_bit_extract_u32 i32:$src0, i32:$src1,
1490 def : BFEPattern <BFE_UINT_eg>;
1492 def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", [], VecALU>;
1493 defm : BFIPatterns <BFI_INT_eg>;
1495 def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24",
1496 [(set i32:$dst, (add (mul U24:$src0, U24:$src1), i32:$src2))], VecALU
1498 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>;
1499 def : ROTRPattern <BIT_ALIGN_INT_eg>;
1501 def MULADD_eg : MULADD_Common<0x14>;
1502 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;
1503 def ASHR_eg : ASHR_Common<0x15>;
1504 def LSHR_eg : LSHR_Common<0x16>;
1505 def LSHL_eg : LSHL_Common<0x17>;
1506 def CNDE_eg : CNDE_Common<0x19>;
1507 def CNDGT_eg : CNDGT_Common<0x1A>;
1508 def CNDGE_eg : CNDGE_Common<0x1B>;
1509 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
1510 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
1511 def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24",
1512 [(set i32:$dst, (mul U24:$src0, U24:$src1))], VecALU
1514 def DOT4_eg : DOT4_Common<0xBE>;
1515 defm CUBE_eg : CUBE_Common<0xC0>;
1517 let hasSideEffects = 1 in {
1518 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", []>;
1521 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
1523 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
1526 let Itinerary = AnyALU;
1529 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
1531 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
1535 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
1537 def GROUP_BARRIER : InstR600 <
1538 (outs), (ins), " GROUP_BARRIER", [(int_AMDGPU_barrier_local)], AnyALU>,
1540 R600ALU_Word1_OP2 <0x54> {
1556 let bank_swizzle = 0;
1558 let update_exec_mask = 0;
1559 let update_pred = 0;
1561 let Inst{31-0} = Word0;
1562 let Inst{63-32} = Word1;
1567 //===----------------------------------------------------------------------===//
1569 //===----------------------------------------------------------------------===//
1570 class R600_LDS <bits<6> op, dag outs, dag ins, string asm,
1571 list<dag> pattern = []> :
1573 InstR600 <outs, ins, asm, pattern, XALU>,
1580 let Word1{27} = offset{0};
1581 let Word1{12} = offset{1};
1582 let Word1{28} = offset{2};
1583 let Word1{31} = offset{3};
1584 let Word0{12} = offset{4};
1585 let Word0{25} = offset{5};
1588 let Inst{31-0} = Word0;
1589 let Inst{63-32} = Word1;
1592 let HasNativeOperands = 1;
1593 let UseNamedOperandTable = 1;
1596 class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS <
1598 (outs R600_Reg32:$dst),
1599 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
1600 LAST:$last, R600_Pred:$pred_sel,
1601 BANK_SWIZZLE:$bank_swizzle),
1602 " "#name#" $last OQAP, $src0$src0_rel $pred_sel",
1612 let usesCustomInserter = 1;
1614 let DisableEncoding = "$dst";
1617 class R600_LDS_1A1D <bits<6> lds_op, string name, list<dag> pattern> :
1621 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
1622 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
1623 LAST:$last, R600_Pred:$pred_sel,
1624 BANK_SWIZZLE:$bank_swizzle),
1625 " "#name#" $last $src0$src0_rel, $src1$src1_rel, $pred_sel",
1634 def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET",
1635 [(set (i32 R600_Reg32:$dst), (local_load R600_Reg32:$src0))]
1638 def LDS_WRITE : R600_LDS_1A1D <0xD, "LDS_WRITE",
1639 [(local_store (i32 R600_Reg32:$src1), R600_Reg32:$src0)]
1642 // TRUNC is used for the FLT_TO_INT instructions to work around a
1643 // perceived problem where the rounding modes are applied differently
1644 // depending on the instruction and the slot they are in.
1646 // https://bugs.freedesktop.org/show_bug.cgi?id=50232
1647 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
1649 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
1650 // which do not need to be truncated since the fp values are 0.0f or 1.0f.
1651 // We should look into handling these cases separately.
1652 def : Pat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>;
1654 def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>;
1657 def : SHA256MaPattern <BFI_INT_eg, XOR_INT>;
1659 def EG_ExportSwz : ExportSwzInst {
1660 let Word1{19-16} = 0; // BURST_COUNT
1661 let Word1{20} = 1; // VALID_PIXEL_MODE
1662 let Word1{21} = eop;
1663 let Word1{29-22} = inst;
1664 let Word1{30} = 0; // MARK
1665 let Word1{31} = 1; // BARRIER
1667 defm : ExportPattern<EG_ExportSwz, 83>;
1669 def EG_ExportBuf : ExportBufInst {
1670 let Word1{19-16} = 0; // BURST_COUNT
1671 let Word1{20} = 1; // VALID_PIXEL_MODE
1672 let Word1{21} = eop;
1673 let Word1{29-22} = inst;
1674 let Word1{30} = 0; // MARK
1675 let Word1{31} = 1; // BARRIER
1677 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
1679 def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT),
1680 "TEX $COUNT @$ADDR"> {
1683 def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT),
1684 "VTX $COUNT @$ADDR"> {
1687 def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR),
1688 "LOOP_START_DX10 @$ADDR"> {
1692 def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1696 def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR),
1697 "LOOP_BREAK @$ADDR"> {
1701 def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR),
1702 "CONTINUE @$ADDR"> {
1706 def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1707 "JUMP @$ADDR POP:$POP_COUNT"> {
1710 def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1711 "ELSE @$ADDR POP:$POP_COUNT"> {
1714 def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> {
1719 def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1720 "POP @$ADDR POP:$POP_COUNT"> {
1723 def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> {
1727 let END_OF_PROGRAM = 1;
1730 } // End Predicates = [isEGorCayman]
1732 //===----------------------------------------------------------------------===//
1733 // Regist loads and stores - for indirect addressing
1734 //===----------------------------------------------------------------------===//
1736 defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>;
1738 //===----------------------------------------------------------------------===//
1739 // Cayman Instructions
1740 //===----------------------------------------------------------------------===//
1742 let Predicates = [isCayman] in {
1744 def MULADD_INT24_cm : R600_3OP <0x08, "MULADD_INT24",
1745 [(set i32:$dst, (add (mul I24:$src0, I24:$src1), i32:$src2))], VecALU
1747 def MUL_INT24_cm : R600_2OP <0x5B, "MUL_INT24",
1748 [(set i32:$dst, (mul I24:$src0, I24:$src1))], VecALU
1751 let isVector = 1 in {
1753 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
1755 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
1756 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
1757 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
1758 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
1759 def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;
1760 def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;
1761 def LOG_IEEE_cm : LOG_IEEE_Common<0x83>;
1762 def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;
1763 def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;
1764 def SIN_cm : SIN_Common<0x8D>;
1765 def COS_cm : COS_Common<0x8E>;
1766 } // End isVector = 1
1768 def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>;
1770 defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;
1772 // RECIP_UINT emulation for Cayman
1773 // The multiplication scales from [0,1] to the unsigned integer range
1775 (AMDGPUurecip i32:$src0),
1776 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)),
1777 (MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1)))
1780 def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> {
1786 def : Pat<(fsqrt f32:$src), (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm $src))>;
1789 class RAT_STORE_DWORD_cm <bits<4> mask, dag ins, list<dag> pat> : EG_CF_RAT <
1790 0x57, 0x14, mask, (outs), ins,
1791 "EXPORT_RAT_INST_STORE_DWORD $rw_gpr, $index_gpr", pat
1793 let eop = 0; // This bit is not used on Cayman.
1796 def RAT_STORE_DWORD32_cm : RAT_STORE_DWORD_cm <0x1,
1797 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr),
1798 [(global_store i32:$rw_gpr, i32:$index_gpr)]
1801 def RAT_STORE_DWORD64_cm : RAT_STORE_DWORD_cm <0x3,
1802 (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr),
1803 [(global_store v2i32:$rw_gpr, i32:$index_gpr)]
1806 class VTX_READ_cm <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
1807 : VTX_WORD0_cm, VTX_READ<name, buffer_id, outs, pattern> {
1812 let FETCH_WHOLE_QUAD = 0;
1813 let BUFFER_ID = buffer_id;
1815 // XXX: We can infer this field based on the SRC_GPR. This would allow us
1816 // to store vertex addresses in any channel, not just X.
1819 let STRUCTURED_READ = 0;
1821 let COALESCED_READ = 0;
1823 let Inst{31-0} = Word0;
1826 class VTX_READ_8_cm <bits<8> buffer_id, list<dag> pattern>
1827 : VTX_READ_cm <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id,
1828 (outs R600_TReg32_X:$dst_gpr), pattern> {
1831 let DST_SEL_Y = 7; // Masked
1832 let DST_SEL_Z = 7; // Masked
1833 let DST_SEL_W = 7; // Masked
1834 let DATA_FORMAT = 1; // FMT_8
1837 class VTX_READ_16_cm <bits<8> buffer_id, list<dag> pattern>
1838 : VTX_READ_cm <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id,
1839 (outs R600_TReg32_X:$dst_gpr), pattern> {
1841 let DST_SEL_Y = 7; // Masked
1842 let DST_SEL_Z = 7; // Masked
1843 let DST_SEL_W = 7; // Masked
1844 let DATA_FORMAT = 5; // FMT_16
1848 class VTX_READ_32_cm <bits<8> buffer_id, list<dag> pattern>
1849 : VTX_READ_cm <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id,
1850 (outs R600_TReg32_X:$dst_gpr), pattern> {
1853 let DST_SEL_Y = 7; // Masked
1854 let DST_SEL_Z = 7; // Masked
1855 let DST_SEL_W = 7; // Masked
1856 let DATA_FORMAT = 0xD; // COLOR_32
1858 // This is not really necessary, but there were some GPU hangs that appeared
1859 // to be caused by ALU instructions in the next instruction group that wrote
1860 // to the $src_gpr registers of the VTX_READ.
1862 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
1863 // %T2_X<def> = MOV %ZERO
1864 //Adding this constraint prevents this from happening.
1865 let Constraints = "$src_gpr.ptr = $dst_gpr";
1868 class VTX_READ_64_cm <bits<8> buffer_id, list<dag> pattern>
1869 : VTX_READ_cm <"VTX_READ_64 $dst_gpr, $src_gpr", buffer_id,
1870 (outs R600_Reg64:$dst_gpr), pattern> {
1876 let DATA_FORMAT = 0x1D; // COLOR_32_32
1879 class VTX_READ_128_cm <bits<8> buffer_id, list<dag> pattern>
1880 : VTX_READ_cm <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id,
1881 (outs R600_Reg128:$dst_gpr), pattern> {
1887 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
1889 // XXX: Need to force VTX_READ_128 instructions to write to the same register
1890 // that holds its buffer address to avoid potential hangs. We can't use
1891 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
1892 // registers are different sizes.
1895 //===----------------------------------------------------------------------===//
1896 // VTX Read from parameter memory space
1897 //===----------------------------------------------------------------------===//
1898 def VTX_READ_PARAM_8_cm : VTX_READ_8_cm <0,
1899 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))]
1902 def VTX_READ_PARAM_16_cm : VTX_READ_16_cm <0,
1903 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))]
1906 def VTX_READ_PARAM_32_cm : VTX_READ_32_cm <0,
1907 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1910 def VTX_READ_PARAM_64_cm : VTX_READ_64_cm <0,
1911 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1914 def VTX_READ_PARAM_128_cm : VTX_READ_128_cm <0,
1915 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1918 //===----------------------------------------------------------------------===//
1919 // VTX Read from global memory space
1920 //===----------------------------------------------------------------------===//
1923 def VTX_READ_GLOBAL_8_cm : VTX_READ_8_cm <1,
1924 [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))]
1927 def VTX_READ_GLOBAL_16_cm : VTX_READ_16_cm <1,
1928 [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))]
1932 def VTX_READ_GLOBAL_32_cm : VTX_READ_32_cm <1,
1933 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1937 def VTX_READ_GLOBAL_64_cm : VTX_READ_64_cm <1,
1938 [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1942 def VTX_READ_GLOBAL_128_cm : VTX_READ_128_cm <1,
1943 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1948 //===----------------------------------------------------------------------===//
1949 // Branch Instructions
1950 //===----------------------------------------------------------------------===//
1953 def IF_PREDICATE_SET : ILFormat<(outs), (ins GPRI32:$src),
1954 "IF_PREDICATE_SET $src", []>;
1956 //===----------------------------------------------------------------------===//
1957 // Pseudo instructions
1958 //===----------------------------------------------------------------------===//
1960 let isPseudo = 1 in {
1962 def PRED_X : InstR600 <
1963 (outs R600_Predicate_Bit:$dst),
1964 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
1966 let FlagOperandIdx = 3;
1969 let isTerminator = 1, isBranch = 1 in {
1970 def JUMP_COND : InstR600 <
1972 (ins brtarget:$target, R600_Predicate_Bit:$p),
1973 "JUMP $target ($p)",
1977 def JUMP : InstR600 <
1979 (ins brtarget:$target),
1984 let isPredicable = 1;
1988 } // End isTerminator = 1, isBranch = 1
1990 let usesCustomInserter = 1 in {
1992 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
1994 def MASK_WRITE : AMDGPUShaderInst <
1996 (ins R600_Reg32:$src),
2001 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 1
2005 (outs R600_Reg128:$dst),
2006 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
2007 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
2008 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
2009 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2,
2010 imm:$resourceId, imm:$samplerId, imm:$textureTarget))],
2015 def TXD_SHADOW: InstR600 <
2016 (outs R600_Reg128:$dst),
2017 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
2018 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
2019 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
2020 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2,
2021 imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))],
2026 } // End isPseudo = 1
2027 } // End usesCustomInserter = 1
2029 def CLAMP_R600 : CLAMP <R600_Reg32>;
2030 def FABS_R600 : FABS<R600_Reg32>;
2031 def FNEG_R600 : FNEG<R600_Reg32>;
2033 //===---------------------------------------------------------------------===//
2034 // Return instruction
2035 //===---------------------------------------------------------------------===//
2036 let isTerminator = 1, isReturn = 1, hasCtrlDep = 1,
2037 usesCustomInserter = 1 in {
2038 def RETURN : ILFormat<(outs), (ins variable_ops),
2039 "RETURN", [(IL_retflag)]>;
2043 //===----------------------------------------------------------------------===//
2044 // Constant Buffer Addressing Support
2045 //===----------------------------------------------------------------------===//
2047 let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
2048 def CONST_COPY : Instruction {
2049 let OutOperandList = (outs R600_Reg32:$dst);
2050 let InOperandList = (ins i32imm:$src);
2052 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
2053 let AsmString = "CONST_COPY";
2054 let neverHasSideEffects = 1;
2055 let isAsCheapAsAMove = 1;
2056 let Itinerary = NullALU;
2058 } // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
2060 def TEX_VTX_CONSTBUF :
2061 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "VTX_READ_eg $dst, $ptr",
2062 [(set v4i32:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$BUFFER_ID)))]>,
2063 VTX_WORD1_GPR, VTX_WORD0_eg {
2067 let FETCH_WHOLE_QUAD = 0;
2071 let USE_CONST_FIELDS = 0;
2072 let NUM_FORMAT_ALL = 2;
2073 let FORMAT_COMP_ALL = 1;
2074 let SRF_MODE_ALL = 1;
2075 let MEGA_FETCH_COUNT = 16;
2080 let DATA_FORMAT = 35;
2082 let Inst{31-0} = Word0;
2083 let Inst{63-32} = Word1;
2085 // LLVM can only encode 64-bit instructions, so these fields are manually
2086 // encoded in R600CodeEmitter
2089 // bits<2> ENDIAN_SWAP = 0;
2090 // bits<1> CONST_BUF_NO_STRIDE = 0;
2091 // bits<1> MEGA_FETCH = 0;
2092 // bits<1> ALT_CONST = 0;
2093 // bits<2> BUFFER_INDEX_MODE = 0;
2097 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
2098 // is done in R600CodeEmitter
2100 // Inst{79-64} = OFFSET;
2101 // Inst{81-80} = ENDIAN_SWAP;
2102 // Inst{82} = CONST_BUF_NO_STRIDE;
2103 // Inst{83} = MEGA_FETCH;
2104 // Inst{84} = ALT_CONST;
2105 // Inst{86-85} = BUFFER_INDEX_MODE;
2106 // Inst{95-86} = 0; Reserved
2108 // VTX_WORD3 (Padding)
2110 // Inst{127-96} = 0;
2115 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr",
2116 [(set v4f32:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>,
2117 VTX_WORD1_GPR, VTX_WORD0_eg {
2121 let FETCH_WHOLE_QUAD = 0;
2125 let USE_CONST_FIELDS = 1;
2126 let NUM_FORMAT_ALL = 0;
2127 let FORMAT_COMP_ALL = 0;
2128 let SRF_MODE_ALL = 1;
2129 let MEGA_FETCH_COUNT = 16;
2134 let DATA_FORMAT = 0;
2136 let Inst{31-0} = Word0;
2137 let Inst{63-32} = Word1;
2139 // LLVM can only encode 64-bit instructions, so these fields are manually
2140 // encoded in R600CodeEmitter
2143 // bits<2> ENDIAN_SWAP = 0;
2144 // bits<1> CONST_BUF_NO_STRIDE = 0;
2145 // bits<1> MEGA_FETCH = 0;
2146 // bits<1> ALT_CONST = 0;
2147 // bits<2> BUFFER_INDEX_MODE = 0;
2151 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
2152 // is done in R600CodeEmitter
2154 // Inst{79-64} = OFFSET;
2155 // Inst{81-80} = ENDIAN_SWAP;
2156 // Inst{82} = CONST_BUF_NO_STRIDE;
2157 // Inst{83} = MEGA_FETCH;
2158 // Inst{84} = ALT_CONST;
2159 // Inst{86-85} = BUFFER_INDEX_MODE;
2160 // Inst{95-86} = 0; Reserved
2162 // VTX_WORD3 (Padding)
2164 // Inst{127-96} = 0;
2170 //===--------------------------------------------------------------------===//
2171 // Instructions support
2172 //===--------------------------------------------------------------------===//
2173 //===---------------------------------------------------------------------===//
2174 // Custom Inserter for Branches and returns, this eventually will be a
2176 //===---------------------------------------------------------------------===//
2177 let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
2178 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
2179 "; Pseudo unconditional branch instruction",
2181 defm BRANCH_COND : BranchConditional<IL_brcond>;
2184 //===---------------------------------------------------------------------===//
2185 // Flow and Program control Instructions
2186 //===---------------------------------------------------------------------===//
2187 let isTerminator=1 in {
2188 def SWITCH : ILFormat< (outs), (ins GPRI32:$src),
2189 !strconcat("SWITCH", " $src"), []>;
2190 def CASE : ILFormat< (outs), (ins GPRI32:$src),
2191 !strconcat("CASE", " $src"), []>;
2192 def BREAK : ILFormat< (outs), (ins),
2194 def CONTINUE : ILFormat< (outs), (ins),
2196 def DEFAULT : ILFormat< (outs), (ins),
2198 def ELSE : ILFormat< (outs), (ins),
2200 def ENDSWITCH : ILFormat< (outs), (ins),
2202 def ENDMAIN : ILFormat< (outs), (ins),
2204 def END : ILFormat< (outs), (ins),
2206 def ENDFUNC : ILFormat< (outs), (ins),
2208 def ENDIF : ILFormat< (outs), (ins),
2210 def WHILELOOP : ILFormat< (outs), (ins),
2212 def ENDLOOP : ILFormat< (outs), (ins),
2214 def FUNC : ILFormat< (outs), (ins),
2216 def RETDYN : ILFormat< (outs), (ins),
2218 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2219 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">;
2220 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2221 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">;
2222 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2223 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">;
2224 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2225 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">;
2226 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2227 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">;
2228 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2229 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">;
2230 defm IFC : BranchInstr2<"IFC">;
2231 defm BREAKC : BranchInstr2<"BREAKC">;
2232 defm CONTINUEC : BranchInstr2<"CONTINUEC">;
2235 //===----------------------------------------------------------------------===//
2237 //===----------------------------------------------------------------------===//
2239 // CND*_INT Pattterns for f32 True / False values
2241 class CND_INT_f32 <InstR600 cnd, CondCode cc> : Pat <
2242 (selectcc i32:$src0, 0, f32:$src1, f32:$src2, cc),
2243 (cnd $src0, $src1, $src2)
2246 def : CND_INT_f32 <CNDE_INT, SETEQ>;
2247 def : CND_INT_f32 <CNDGT_INT, SETGT>;
2248 def : CND_INT_f32 <CNDGE_INT, SETGE>;
2250 //CNDGE_INT extra pattern
2252 (selectcc i32:$src0, -1, i32:$src1, i32:$src2, COND_GT),
2253 (CNDGE_INT $src0, $src1, $src2)
2259 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
2263 (int_AMDGPU_kill f32:$src0),
2264 (MASK_WRITE (KILLGT (f32 ZERO), $src0))
2269 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_LT),
2275 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_LE),
2279 // SETGT_DX10 reverse args
2281 (selectcc f32:$src0, f32:$src1, -1, 0, COND_LT),
2282 (SETGT_DX10 $src1, $src0)
2285 // SETGE_DX10 reverse args
2287 (selectcc f32:$src0, f32:$src1, -1, 0, COND_LE),
2288 (SETGE_DX10 $src1, $src0)
2291 // SETGT_INT reverse args
2293 (selectcc i32:$src0, i32:$src1, -1, 0, SETLT),
2294 (SETGT_INT $src1, $src0)
2297 // SETGE_INT reverse args
2299 (selectcc i32:$src0, i32:$src1, -1, 0, SETLE),
2300 (SETGE_INT $src1, $src0)
2303 // SETGT_UINT reverse args
2305 (selectcc i32:$src0, i32:$src1, -1, 0, SETULT),
2306 (SETGT_UINT $src1, $src0)
2309 // SETGE_UINT reverse args
2311 (selectcc i32:$src0, i32:$src1, -1, 0, SETULE),
2312 (SETGE_UINT $src1, $src0)
2315 // The next two patterns are special cases for handling 'true if ordered' and
2316 // 'true if unordered' conditionals. The assumption here is that the behavior of
2317 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
2319 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
2320 // We assume that SETE returns false when one of the operands is NAN and
2321 // SNE returns true when on of the operands is NAN
2323 //SETE - 'true if ordered'
2325 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, SETO),
2329 //SETE_DX10 - 'true if ordered'
2331 (selectcc f32:$src0, f32:$src1, -1, 0, SETO),
2332 (SETE_DX10 $src0, $src1)
2335 //SNE - 'true if unordered'
2337 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, SETUO),
2341 //SETNE_DX10 - 'true if ordered'
2343 (selectcc f32:$src0, f32:$src1, -1, 0, SETUO),
2344 (SETNE_DX10 $src0, $src1)
2347 def : Extract_Element <f32, v4f32, 0, sub0>;
2348 def : Extract_Element <f32, v4f32, 1, sub1>;
2349 def : Extract_Element <f32, v4f32, 2, sub2>;
2350 def : Extract_Element <f32, v4f32, 3, sub3>;
2352 def : Insert_Element <f32, v4f32, 0, sub0>;
2353 def : Insert_Element <f32, v4f32, 1, sub1>;
2354 def : Insert_Element <f32, v4f32, 2, sub2>;
2355 def : Insert_Element <f32, v4f32, 3, sub3>;
2357 def : Extract_Element <i32, v4i32, 0, sub0>;
2358 def : Extract_Element <i32, v4i32, 1, sub1>;
2359 def : Extract_Element <i32, v4i32, 2, sub2>;
2360 def : Extract_Element <i32, v4i32, 3, sub3>;
2362 def : Insert_Element <i32, v4i32, 0, sub0>;
2363 def : Insert_Element <i32, v4i32, 1, sub1>;
2364 def : Insert_Element <i32, v4i32, 2, sub2>;
2365 def : Insert_Element <i32, v4i32, 3, sub3>;
2367 def : Vector4_Build <v4f32, f32>;
2368 def : Vector4_Build <v4i32, i32>;
2370 def : Extract_Element <f32, v2f32, 0, sub0>;
2371 def : Extract_Element <f32, v2f32, 1, sub1>;
2373 def : Insert_Element <f32, v2f32, 0, sub0>;
2374 def : Insert_Element <f32, v2f32, 1, sub1>;
2376 def : Extract_Element <i32, v2i32, 0, sub0>;
2377 def : Extract_Element <i32, v2i32, 1, sub1>;
2379 def : Insert_Element <i32, v2i32, 0, sub0>;
2380 def : Insert_Element <i32, v2i32, 1, sub1>;
2382 // bitconvert patterns
2384 def : BitConvert <i32, f32, R600_Reg32>;
2385 def : BitConvert <f32, i32, R600_Reg32>;
2386 def : BitConvert <v2f32, v2i32, R600_Reg64>;
2387 def : BitConvert <v2i32, v2f32, R600_Reg64>;
2388 def : BitConvert <v4f32, v4i32, R600_Reg128>;
2389 def : BitConvert <v4i32, v4f32, R600_Reg128>;
2391 // DWORDADDR pattern
2392 def : DwordAddrPat <i32, R600_Reg32>;
2394 } // End isR600toCayman Predicate