1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for R600InstrInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef R600INSTRUCTIONINFO_H_
16 #define R600INSTRUCTIONINFO_H_
18 #include "AMDGPUInstrInfo.h"
20 #include "R600Defines.h"
21 #include "R600RegisterInfo.h"
26 class AMDGPUTargetMachine;
29 class MachineFunction;
31 class MachineInstrBuilder;
33 class R600InstrInfo : public AMDGPUInstrInfo {
35 const R600RegisterInfo RI;
37 int getBranchInstr(const MachineOperand &op) const;
40 explicit R600InstrInfo(AMDGPUTargetMachine &tm);
42 const R600RegisterInfo &getRegisterInfo() const;
43 virtual void copyPhysReg(MachineBasicBlock &MBB,
44 MachineBasicBlock::iterator MI, DebugLoc DL,
45 unsigned DestReg, unsigned SrcReg,
48 bool isTrig(const MachineInstr &MI) const;
49 bool isPlaceHolderOpcode(unsigned opcode) const;
50 bool isReductionOp(unsigned opcode) const;
51 bool isCubeOp(unsigned opcode) const;
53 /// \returns true if this \p Opcode represents an ALU instruction.
54 bool isALUInstr(unsigned Opcode) const;
56 /// \breif Vector instructions are instructions that must fill all
57 /// instruction slots within an instruction group.
58 bool isVector(const MachineInstr &MI) const;
60 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
63 virtual unsigned getIEQOpcode() const;
64 virtual bool isMov(unsigned Opcode) const;
66 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
67 const ScheduleDAG *DAG) const;
69 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
71 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
72 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
74 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
76 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
78 bool isPredicated(const MachineInstr *MI) const;
80 bool isPredicable(MachineInstr *MI) const;
83 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
84 const BranchProbability &Probability) const;
86 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
87 unsigned ExtraPredCycles,
88 const BranchProbability &Probability) const ;
91 isProfitableToIfCvt(MachineBasicBlock &TMBB,
92 unsigned NumTCycles, unsigned ExtraTCycles,
93 MachineBasicBlock &FMBB,
94 unsigned NumFCycles, unsigned ExtraFCycles,
95 const BranchProbability &Probability) const;
97 bool DefinesPredicate(MachineInstr *MI,
98 std::vector<MachineOperand> &Pred) const;
100 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
101 const SmallVectorImpl<MachineOperand> &Pred2) const;
103 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
104 MachineBasicBlock &FMBB) const;
106 bool PredicateInstruction(MachineInstr *MI,
107 const SmallVectorImpl<MachineOperand> &Pred) const;
109 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
110 const MachineInstr *MI,
111 unsigned *PredCost = 0) const;
113 virtual int getInstrLatency(const InstrItineraryData *ItinData,
114 SDNode *Node) const { return 1;}
116 /// \returns a list of all the registers that may be accesed using indirect
118 std::vector<unsigned> getIndirectReservedRegs(const MachineFunction &MF) const;
120 virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
122 virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
125 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
126 unsigned Channel) const;
128 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
129 unsigned SourceReg) const;
131 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
133 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
134 MachineBasicBlock::iterator I,
135 unsigned ValueReg, unsigned Address,
136 unsigned OffsetReg) const;
138 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
139 MachineBasicBlock::iterator I,
140 unsigned ValueReg, unsigned Address,
141 unsigned OffsetReg) const;
143 virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
146 ///buildDefaultInstruction - This function returns a MachineInstr with
147 /// all the instruction modifiers initialized to their default values.
148 /// You can use this function to avoid manually specifying each instruction
149 /// modifier operand when building a new instruction.
151 /// \returns a MachineInstr with all the instruction modifiers initialized
152 /// to their default values.
153 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
154 MachineBasicBlock::iterator I,
158 unsigned Src1Reg = 0) const;
160 MachineInstr *buildMovImm(MachineBasicBlock &BB,
161 MachineBasicBlock::iterator I,
165 /// \brief Get the index of Op in the MachineInstr.
167 /// \returns -1 if the Instruction does not contain the specified \p Op.
168 int getOperandIdx(const MachineInstr &MI, R600Operands::Ops Op) const;
170 /// \brief Get the index of \p Op for the given Opcode.
172 /// \returns -1 if the Instruction does not contain the specified \p Op.
173 int getOperandIdx(unsigned Opcode, R600Operands::Ops Op) const;
175 /// \brief Helper function for setting instruction flag values.
176 void setImmOperand(MachineInstr *MI, R600Operands::Ops Op, int64_t Imm) const;
178 /// \returns true if this instruction has an operand for storing target flags.
179 bool hasFlagOperand(const MachineInstr &MI) const;
181 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
182 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
184 ///\brief Determine if the specified \p Flag is set on this \p Operand.
185 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
187 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
188 /// \param Flag The flag being set.
190 /// \returns the operand containing the flags for this instruction.
191 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
192 unsigned Flag = 0) const;
194 /// \brief Clear the specified flag on the instruction.
195 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
198 } // End llvm namespace
200 #endif // R600INSTRINFO_H_