1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for R600InstrInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef R600INSTRUCTIONINFO_H_
16 #define R600INSTRUCTIONINFO_H_
18 #include "AMDGPUInstrInfo.h"
20 #include "R600Defines.h"
21 #include "R600RegisterInfo.h"
26 class AMDGPUTargetMachine;
29 class MachineFunction;
31 class MachineInstrBuilder;
33 class R600InstrInfo : public AMDGPUInstrInfo {
35 const R600RegisterInfo RI;
37 int getBranchInstr(const MachineOperand &op) const;
40 explicit R600InstrInfo(AMDGPUTargetMachine &tm);
42 const R600RegisterInfo &getRegisterInfo() const;
43 virtual void copyPhysReg(MachineBasicBlock &MBB,
44 MachineBasicBlock::iterator MI, DebugLoc DL,
45 unsigned DestReg, unsigned SrcReg,
48 bool isTrig(const MachineInstr &MI) const;
49 bool isPlaceHolderOpcode(unsigned opcode) const;
50 bool isReductionOp(unsigned opcode) const;
51 bool isCubeOp(unsigned opcode) const;
53 /// \returns true if this \p Opcode represents an ALU instruction.
54 bool isALUInstr(unsigned Opcode) const;
56 bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
57 bool canBundle(const std::vector<MachineInstr *> &) const;
59 /// \breif Vector instructions are instructions that must fill all
60 /// instruction slots within an instruction group.
61 bool isVector(const MachineInstr &MI) const;
63 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
66 virtual unsigned getIEQOpcode() const;
67 virtual bool isMov(unsigned Opcode) const;
69 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
70 const ScheduleDAG *DAG) const;
72 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
74 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
75 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
77 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
79 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
81 bool isPredicated(const MachineInstr *MI) const;
83 bool isPredicable(MachineInstr *MI) const;
86 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
87 const BranchProbability &Probability) const;
89 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
90 unsigned ExtraPredCycles,
91 const BranchProbability &Probability) const ;
94 isProfitableToIfCvt(MachineBasicBlock &TMBB,
95 unsigned NumTCycles, unsigned ExtraTCycles,
96 MachineBasicBlock &FMBB,
97 unsigned NumFCycles, unsigned ExtraFCycles,
98 const BranchProbability &Probability) const;
100 bool DefinesPredicate(MachineInstr *MI,
101 std::vector<MachineOperand> &Pred) const;
103 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
104 const SmallVectorImpl<MachineOperand> &Pred2) const;
106 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
107 MachineBasicBlock &FMBB) const;
109 bool PredicateInstruction(MachineInstr *MI,
110 const SmallVectorImpl<MachineOperand> &Pred) const;
112 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
113 const MachineInstr *MI,
114 unsigned *PredCost = 0) const;
116 virtual int getInstrLatency(const InstrItineraryData *ItinData,
117 SDNode *Node) const { return 1;}
119 /// \returns a list of all the registers that may be accesed using indirect
121 std::vector<unsigned> getIndirectReservedRegs(const MachineFunction &MF) const;
123 virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
125 virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
128 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
129 unsigned Channel) const;
131 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
132 unsigned SourceReg) const;
134 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
136 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
137 MachineBasicBlock::iterator I,
138 unsigned ValueReg, unsigned Address,
139 unsigned OffsetReg) const;
141 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
142 MachineBasicBlock::iterator I,
143 unsigned ValueReg, unsigned Address,
144 unsigned OffsetReg) const;
146 virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
148 unsigned getMaxAlusPerClause() const;
150 ///buildDefaultInstruction - This function returns a MachineInstr with
151 /// all the instruction modifiers initialized to their default values.
152 /// You can use this function to avoid manually specifying each instruction
153 /// modifier operand when building a new instruction.
155 /// \returns a MachineInstr with all the instruction modifiers initialized
156 /// to their default values.
157 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
158 MachineBasicBlock::iterator I,
162 unsigned Src1Reg = 0) const;
164 MachineInstr *buildMovImm(MachineBasicBlock &BB,
165 MachineBasicBlock::iterator I,
169 /// \brief Get the index of Op in the MachineInstr.
171 /// \returns -1 if the Instruction does not contain the specified \p Op.
172 int getOperandIdx(const MachineInstr &MI, R600Operands::Ops Op) const;
174 /// \brief Get the index of \p Op for the given Opcode.
176 /// \returns -1 if the Instruction does not contain the specified \p Op.
177 int getOperandIdx(unsigned Opcode, R600Operands::Ops Op) const;
179 /// \brief Helper function for setting instruction flag values.
180 void setImmOperand(MachineInstr *MI, R600Operands::Ops Op, int64_t Imm) const;
182 /// \returns true if this instruction has an operand for storing target flags.
183 bool hasFlagOperand(const MachineInstr &MI) const;
185 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
186 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
188 ///\brief Determine if the specified \p Flag is set on this \p Operand.
189 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
191 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
192 /// \param Flag The flag being set.
194 /// \returns the operand containing the flags for this instruction.
195 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
196 unsigned Flag = 0) const;
198 /// \brief Clear the specified flag on the instruction.
199 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
202 } // End llvm namespace
204 #endif // R600INSTRINFO_H_