1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for R600InstrInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef R600INSTRUCTIONINFO_H_
16 #define R600INSTRUCTIONINFO_H_
18 #include "AMDGPUInstrInfo.h"
19 #include "R600Defines.h"
20 #include "R600RegisterInfo.h"
25 class AMDGPUTargetMachine;
28 class MachineFunction;
30 class MachineInstrBuilder;
32 class R600InstrInfo : public AMDGPUInstrInfo {
34 const R600RegisterInfo RI;
35 const AMDGPUSubtarget &ST;
37 int getBranchInstr(const MachineOperand &op) const;
38 std::vector<std::pair<int, unsigned> >
39 ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV) const;
51 explicit R600InstrInfo(AMDGPUTargetMachine &tm);
53 const R600RegisterInfo &getRegisterInfo() const;
54 virtual void copyPhysReg(MachineBasicBlock &MBB,
55 MachineBasicBlock::iterator MI, DebugLoc DL,
56 unsigned DestReg, unsigned SrcReg,
59 bool isTrig(const MachineInstr &MI) const;
60 bool isPlaceHolderOpcode(unsigned opcode) const;
61 bool isReductionOp(unsigned opcode) const;
62 bool isCubeOp(unsigned opcode) const;
64 /// \returns true if this \p Opcode represents an ALU instruction.
65 bool isALUInstr(unsigned Opcode) const;
67 bool isTransOnly(unsigned Opcode) const;
68 bool isTransOnly(const MachineInstr *MI) const;
70 bool usesVertexCache(unsigned Opcode) const;
71 bool usesVertexCache(const MachineInstr *MI) const;
72 bool usesTextureCache(unsigned Opcode) const;
73 bool usesTextureCache(const MachineInstr *MI) const;
75 /// \returns a pair for each src of an ALU instructions.
76 /// The first member of a pair is the register id.
77 /// If register is ALU_CONST, second member is SEL.
78 /// If register is ALU_LITERAL, second member is IMM.
79 /// Otherwise, second member value is undefined.
80 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
81 getSrcs(MachineInstr *MI) const;
83 /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
84 /// returns true and the first (in lexical order) BankSwizzle affectation
85 /// starting from the one already provided in the Instruction Group MIs that
86 /// fits Read Port limitations in BS if available. Otherwise returns false
87 /// and undefined content in BS.
88 /// PV holds GPR to PV registers in the Instruction Group MIs.
89 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
90 const DenseMap<unsigned, unsigned> &PV,
91 std::vector<BankSwizzle> &BS) const;
92 bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
93 bool canBundle(const std::vector<MachineInstr *> &) const;
95 /// \breif Vector instructions are instructions that must fill all
96 /// instruction slots within an instruction group.
97 bool isVector(const MachineInstr &MI) const;
99 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
102 virtual unsigned getIEQOpcode() const;
103 virtual bool isMov(unsigned Opcode) const;
105 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
106 const ScheduleDAG *DAG) const;
108 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
110 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
111 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
113 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
115 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
117 bool isPredicated(const MachineInstr *MI) const;
119 bool isPredicable(MachineInstr *MI) const;
122 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
123 const BranchProbability &Probability) const;
125 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
126 unsigned ExtraPredCycles,
127 const BranchProbability &Probability) const ;
130 isProfitableToIfCvt(MachineBasicBlock &TMBB,
131 unsigned NumTCycles, unsigned ExtraTCycles,
132 MachineBasicBlock &FMBB,
133 unsigned NumFCycles, unsigned ExtraFCycles,
134 const BranchProbability &Probability) const;
136 bool DefinesPredicate(MachineInstr *MI,
137 std::vector<MachineOperand> &Pred) const;
139 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
140 const SmallVectorImpl<MachineOperand> &Pred2) const;
142 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
143 MachineBasicBlock &FMBB) const;
145 bool PredicateInstruction(MachineInstr *MI,
146 const SmallVectorImpl<MachineOperand> &Pred) const;
148 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
149 const MachineInstr *MI,
150 unsigned *PredCost = 0) const;
152 virtual int getInstrLatency(const InstrItineraryData *ItinData,
153 SDNode *Node) const { return 1;}
155 /// \returns a list of all the registers that may be accesed using indirect
157 std::vector<unsigned> getIndirectReservedRegs(const MachineFunction &MF) const;
159 virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
161 virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
164 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
165 unsigned Channel) const;
167 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
168 unsigned SourceReg) const;
170 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
172 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
173 MachineBasicBlock::iterator I,
174 unsigned ValueReg, unsigned Address,
175 unsigned OffsetReg) const;
177 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
178 MachineBasicBlock::iterator I,
179 unsigned ValueReg, unsigned Address,
180 unsigned OffsetReg) const;
182 virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
184 unsigned getMaxAlusPerClause() const;
186 ///buildDefaultInstruction - This function returns a MachineInstr with
187 /// all the instruction modifiers initialized to their default values.
188 /// You can use this function to avoid manually specifying each instruction
189 /// modifier operand when building a new instruction.
191 /// \returns a MachineInstr with all the instruction modifiers initialized
192 /// to their default values.
193 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
194 MachineBasicBlock::iterator I,
198 unsigned Src1Reg = 0) const;
200 MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
203 unsigned DstReg) const;
205 MachineInstr *buildMovImm(MachineBasicBlock &BB,
206 MachineBasicBlock::iterator I,
210 /// \brief Get the index of Op in the MachineInstr.
212 /// \returns -1 if the Instruction does not contain the specified \p Op.
213 int getOperandIdx(const MachineInstr &MI, R600Operands::Ops Op) const;
214 int getOperandIdx(const MachineInstr &MI, R600Operands::VecOps Op) const;
216 /// \brief Get the index of \p Op for the given Opcode.
218 /// \returns -1 if the Instruction does not contain the specified \p Op.
219 int getOperandIdx(unsigned Opcode, R600Operands::Ops Op) const;
220 int getOperandIdx(unsigned Opcode, R600Operands::VecOps Op) const;
222 /// \brief Helper function for setting instruction flag values.
223 void setImmOperand(MachineInstr *MI, R600Operands::Ops Op, int64_t Imm) const;
225 /// \returns true if this instruction has an operand for storing target flags.
226 bool hasFlagOperand(const MachineInstr &MI) const;
228 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
229 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
231 ///\brief Determine if the specified \p Flag is set on this \p Operand.
232 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
234 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
235 /// \param Flag The flag being set.
237 /// \returns the operand containing the flags for this instruction.
238 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
239 unsigned Flag = 0) const;
241 /// \brief Clear the specified flag on the instruction.
242 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
245 } // End llvm namespace
247 #endif // R600INSTRINFO_H_