1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for R600InstrInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef R600INSTRUCTIONINFO_H_
16 #define R600INSTRUCTIONINFO_H_
18 #include "AMDGPUInstrInfo.h"
19 #include "R600Defines.h"
20 #include "R600RegisterInfo.h"
25 class AMDGPUTargetMachine;
28 class MachineFunction;
30 class MachineInstrBuilder;
32 class R600InstrInfo : public AMDGPUInstrInfo {
34 const R600RegisterInfo RI;
35 const AMDGPUSubtarget &ST;
37 int getBranchInstr(const MachineOperand &op) const;
38 std::vector<std::pair<int, unsigned> >
39 ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
43 ALU_VEC_012_SCL_210 = 0,
51 explicit R600InstrInfo(AMDGPUTargetMachine &tm);
53 const R600RegisterInfo &getRegisterInfo() const;
54 virtual void copyPhysReg(MachineBasicBlock &MBB,
55 MachineBasicBlock::iterator MI, DebugLoc DL,
56 unsigned DestReg, unsigned SrcReg,
59 bool isTrig(const MachineInstr &MI) const;
60 bool isPlaceHolderOpcode(unsigned opcode) const;
61 bool isReductionOp(unsigned opcode) const;
62 bool isCubeOp(unsigned opcode) const;
64 /// \returns true if this \p Opcode represents an ALU instruction.
65 bool isALUInstr(unsigned Opcode) const;
66 bool hasInstrModifiers(unsigned Opcode) const;
67 bool isLDSInstr(unsigned Opcode) const;
69 bool isTransOnly(unsigned Opcode) const;
70 bool isTransOnly(const MachineInstr *MI) const;
72 bool usesVertexCache(unsigned Opcode) const;
73 bool usesVertexCache(const MachineInstr *MI) const;
74 bool usesTextureCache(unsigned Opcode) const;
75 bool usesTextureCache(const MachineInstr *MI) const;
77 bool mustBeLastInClause(unsigned Opcode) const;
79 /// \returns a pair for each src of an ALU instructions.
80 /// The first member of a pair is the register id.
81 /// If register is ALU_CONST, second member is SEL.
82 /// If register is ALU_LITERAL, second member is IMM.
83 /// Otherwise, second member value is undefined.
84 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
85 getSrcs(MachineInstr *MI) const;
88 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
89 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
90 const std::vector<std::pair<int, unsigned> > &TransSrcs,
91 R600InstrInfo::BankSwizzle TransSwz) const;
93 bool FindSwizzleForVectorSlot(
94 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
95 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
96 const std::vector<std::pair<int, unsigned> > &TransSrcs,
97 R600InstrInfo::BankSwizzle TransSwz) const;
99 /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
100 /// returns true and the first (in lexical order) BankSwizzle affectation
101 /// starting from the one already provided in the Instruction Group MIs that
102 /// fits Read Port limitations in BS if available. Otherwise returns false
103 /// and undefined content in BS.
104 /// isLastAluTrans should be set if the last Alu of MIs will be executed on
105 /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
106 /// apply to the last instruction.
107 /// PV holds GPR to PV registers in the Instruction Group MIs.
108 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
109 const DenseMap<unsigned, unsigned> &PV,
110 std::vector<BankSwizzle> &BS,
111 bool isLastAluTrans) const;
113 /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
114 /// from KCache bank on R700+. This function check if MI set in input meet
116 bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
117 /// Same but using const index set instead of MI set.
118 bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
120 /// \breif Vector instructions are instructions that must fill all
121 /// instruction slots within an instruction group.
122 bool isVector(const MachineInstr &MI) const;
124 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
127 virtual unsigned getIEQOpcode() const;
128 virtual bool isMov(unsigned Opcode) const;
130 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
131 const ScheduleDAG *DAG) const;
133 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
135 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
136 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
138 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
140 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
142 bool isPredicated(const MachineInstr *MI) const;
144 bool isPredicable(MachineInstr *MI) const;
147 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
148 const BranchProbability &Probability) const;
150 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
151 unsigned ExtraPredCycles,
152 const BranchProbability &Probability) const ;
155 isProfitableToIfCvt(MachineBasicBlock &TMBB,
156 unsigned NumTCycles, unsigned ExtraTCycles,
157 MachineBasicBlock &FMBB,
158 unsigned NumFCycles, unsigned ExtraFCycles,
159 const BranchProbability &Probability) const;
161 bool DefinesPredicate(MachineInstr *MI,
162 std::vector<MachineOperand> &Pred) const;
164 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
165 const SmallVectorImpl<MachineOperand> &Pred2) const;
167 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
168 MachineBasicBlock &FMBB) const;
170 bool PredicateInstruction(MachineInstr *MI,
171 const SmallVectorImpl<MachineOperand> &Pred) const;
173 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
174 const MachineInstr *MI,
175 unsigned *PredCost = 0) const;
177 virtual int getInstrLatency(const InstrItineraryData *ItinData,
178 SDNode *Node) const { return 1;}
180 /// \returns a list of all the registers that may be accesed using indirect
182 std::vector<unsigned> getIndirectReservedRegs(const MachineFunction &MF) const;
184 virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
186 virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
189 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
190 unsigned Channel) const;
192 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
193 unsigned SourceReg) const;
195 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
197 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
198 MachineBasicBlock::iterator I,
199 unsigned ValueReg, unsigned Address,
200 unsigned OffsetReg) const;
202 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
203 MachineBasicBlock::iterator I,
204 unsigned ValueReg, unsigned Address,
205 unsigned OffsetReg) const;
207 virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
209 unsigned getMaxAlusPerClause() const;
211 ///buildDefaultInstruction - This function returns a MachineInstr with
212 /// all the instruction modifiers initialized to their default values.
213 /// You can use this function to avoid manually specifying each instruction
214 /// modifier operand when building a new instruction.
216 /// \returns a MachineInstr with all the instruction modifiers initialized
217 /// to their default values.
218 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
219 MachineBasicBlock::iterator I,
223 unsigned Src1Reg = 0) const;
225 MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
228 unsigned DstReg) const;
230 MachineInstr *buildMovImm(MachineBasicBlock &BB,
231 MachineBasicBlock::iterator I,
235 /// \brief Get the index of Op in the MachineInstr.
237 /// \returns -1 if the Instruction does not contain the specified \p Op.
238 int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
240 /// \brief Get the index of \p Op for the given Opcode.
242 /// \returns -1 if the Instruction does not contain the specified \p Op.
243 int getOperandIdx(unsigned Opcode, unsigned Op) const;
245 /// \brief Helper function for setting instruction flag values.
246 void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const;
248 /// \returns true if this instruction has an operand for storing target flags.
249 bool hasFlagOperand(const MachineInstr &MI) const;
251 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
252 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
254 ///\brief Determine if the specified \p Flag is set on this \p Operand.
255 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
257 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
258 /// \param Flag The flag being set.
260 /// \returns the operand containing the flags for this instruction.
261 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
262 unsigned Flag = 0) const;
264 /// \brief Clear the specified flag on the instruction.
265 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
268 } // End llvm namespace
270 #endif // R600INSTRINFO_H_