1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief R600 Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
15 #include "R600InstrInfo.h"
16 #include "AMDGPUSubtarget.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "R600Defines.h"
19 #include "R600MachineFunctionInfo.h"
20 #include "R600RegisterInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #define GET_INSTRINFO_CTOR
26 #include "AMDGPUGenDFAPacketizer.inc"
30 R600InstrInfo::R600InstrInfo(AMDGPUTargetMachine &tm)
31 : AMDGPUInstrInfo(tm),
35 const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const {
39 bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
40 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
43 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
44 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
48 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator MI, DebugLoc DL,
50 unsigned DestReg, unsigned SrcReg,
52 if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
53 && AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
54 for (unsigned I = 0; I < 4; I++) {
55 unsigned SubRegIndex = RI.getSubRegFromChannel(I);
56 buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
57 RI.getSubReg(DestReg, SubRegIndex),
58 RI.getSubReg(SrcReg, SubRegIndex))
60 RegState::Define | RegState::Implicit);
64 // We can't copy vec4 registers
65 assert(!AMDGPU::R600_Reg128RegClass.contains(DestReg)
66 && !AMDGPU::R600_Reg128RegClass.contains(SrcReg));
68 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
70 NewMI->getOperand(getOperandIdx(*NewMI, R600Operands::SRC0))
75 MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF,
76 unsigned DstReg, int64_t Imm) const {
77 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc());
78 MachineInstrBuilder MIB(*MF, MI);
79 MIB.addReg(DstReg, RegState::Define);
80 MIB.addReg(AMDGPU::ALU_LITERAL_X);
82 MIB.addReg(0); // PREDICATE_BIT
87 unsigned R600InstrInfo::getIEQOpcode() const {
88 return AMDGPU::SETE_INT;
91 bool R600InstrInfo::isMov(unsigned Opcode) const {
95 default: return false;
97 case AMDGPU::MOV_IMM_F32:
98 case AMDGPU::MOV_IMM_I32:
103 // Some instructions act as place holders to emulate operations that the GPU
104 // hardware does automatically. This function can be used to check if
105 // an opcode falls into this category.
106 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {
108 default: return false;
114 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
116 default: return false;
117 case AMDGPU::DOT4_r600_pseudo:
118 case AMDGPU::DOT4_eg_pseudo:
123 bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
125 default: return false;
126 case AMDGPU::CUBE_r600_pseudo:
127 case AMDGPU::CUBE_r600_real:
128 case AMDGPU::CUBE_eg_pseudo:
129 case AMDGPU::CUBE_eg_real:
134 bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
135 unsigned TargetFlags = get(Opcode).TSFlags;
137 return ((TargetFlags & R600_InstFlag::OP1) |
138 (TargetFlags & R600_InstFlag::OP2) |
139 (TargetFlags & R600_InstFlag::OP3));
142 DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM,
143 const ScheduleDAG *DAG) const {
144 const InstrItineraryData *II = TM->getInstrItineraryData();
145 return TM->getSubtarget<AMDGPUSubtarget>().createDFAPacketizer(II);
149 isPredicateSetter(unsigned Opcode) {
158 static MachineInstr *
159 findFirstPredicateSetterFrom(MachineBasicBlock &MBB,
160 MachineBasicBlock::iterator I) {
161 while (I != MBB.begin()) {
163 MachineInstr *MI = I;
164 if (isPredicateSetter(MI->getOpcode()))
172 R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
173 MachineBasicBlock *&TBB,
174 MachineBasicBlock *&FBB,
175 SmallVectorImpl<MachineOperand> &Cond,
176 bool AllowModify) const {
177 // Most of the following comes from the ARM implementation of AnalyzeBranch
179 // If the block has no terminators, it just falls into the block after it.
180 MachineBasicBlock::iterator I = MBB.end();
181 if (I == MBB.begin())
184 while (I->isDebugValue()) {
185 if (I == MBB.begin())
189 if (static_cast<MachineInstr *>(I)->getOpcode() != AMDGPU::JUMP) {
193 // Get the last instruction in the block.
194 MachineInstr *LastInst = I;
196 // If there is only one terminator instruction, process it.
197 unsigned LastOpc = LastInst->getOpcode();
198 if (I == MBB.begin() ||
199 static_cast<MachineInstr *>(--I)->getOpcode() != AMDGPU::JUMP) {
200 if (LastOpc == AMDGPU::JUMP) {
201 if(!isPredicated(LastInst)) {
202 TBB = LastInst->getOperand(0).getMBB();
205 MachineInstr *predSet = I;
206 while (!isPredicateSetter(predSet->getOpcode())) {
209 TBB = LastInst->getOperand(0).getMBB();
210 Cond.push_back(predSet->getOperand(1));
211 Cond.push_back(predSet->getOperand(2));
212 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
216 return true; // Can't handle indirect branch.
219 // Get the instruction before it if it is a terminator.
220 MachineInstr *SecondLastInst = I;
221 unsigned SecondLastOpc = SecondLastInst->getOpcode();
223 // If the block ends with a B and a Bcc, handle it.
224 if (SecondLastOpc == AMDGPU::JUMP &&
225 isPredicated(SecondLastInst) &&
226 LastOpc == AMDGPU::JUMP &&
227 !isPredicated(LastInst)) {
228 MachineInstr *predSet = --I;
229 while (!isPredicateSetter(predSet->getOpcode())) {
232 TBB = SecondLastInst->getOperand(0).getMBB();
233 FBB = LastInst->getOperand(0).getMBB();
234 Cond.push_back(predSet->getOperand(1));
235 Cond.push_back(predSet->getOperand(2));
236 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
240 // Otherwise, can't handle this.
244 int R600InstrInfo::getBranchInstr(const MachineOperand &op) const {
245 const MachineInstr *MI = op.getParent();
247 switch (MI->getDesc().OpInfo->RegClass) {
248 default: // FIXME: fallthrough??
249 case AMDGPU::GPRI32RegClassID: return AMDGPU::BRANCH_COND_i32;
250 case AMDGPU::GPRF32RegClassID: return AMDGPU::BRANCH_COND_f32;
255 R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
256 MachineBasicBlock *TBB,
257 MachineBasicBlock *FBB,
258 const SmallVectorImpl<MachineOperand> &Cond,
260 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
264 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB).addReg(0);
267 MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
268 assert(PredSet && "No previous predicate !");
269 addFlag(PredSet, 0, MO_FLAG_PUSH);
270 PredSet->getOperand(2).setImm(Cond[1].getImm());
272 BuildMI(&MBB, DL, get(AMDGPU::JUMP))
274 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
278 MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
279 assert(PredSet && "No previous predicate !");
280 addFlag(PredSet, 0, MO_FLAG_PUSH);
281 PredSet->getOperand(2).setImm(Cond[1].getImm());
282 BuildMI(&MBB, DL, get(AMDGPU::JUMP))
284 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
285 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB).addReg(0);
291 R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
293 // Note : we leave PRED* instructions there.
294 // They may be needed when predicating instructions.
296 MachineBasicBlock::iterator I = MBB.end();
298 if (I == MBB.begin()) {
302 switch (I->getOpcode()) {
306 if (isPredicated(I)) {
307 MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
308 clearFlag(predSet, 0, MO_FLAG_PUSH);
310 I->eraseFromParent();
315 if (I == MBB.begin()) {
319 switch (I->getOpcode()) {
320 // FIXME: only one case??
324 if (isPredicated(I)) {
325 MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
326 clearFlag(predSet, 0, MO_FLAG_PUSH);
328 I->eraseFromParent();
335 R600InstrInfo::isPredicated(const MachineInstr *MI) const {
336 int idx = MI->findFirstPredOperandIdx();
340 unsigned Reg = MI->getOperand(idx).getReg();
342 default: return false;
343 case AMDGPU::PRED_SEL_ONE:
344 case AMDGPU::PRED_SEL_ZERO:
345 case AMDGPU::PREDICATE_BIT:
351 R600InstrInfo::isPredicable(MachineInstr *MI) const {
352 // XXX: KILL* instructions can be predicated, but they must be the last
353 // instruction in a clause, so this means any instructions after them cannot
354 // be predicated. Until we have proper support for instruction clauses in the
355 // backend, we will mark KILL* instructions as unpredicable.
357 if (MI->getOpcode() == AMDGPU::KILLGT) {
360 return AMDGPUInstrInfo::isPredicable(MI);
366 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
368 unsigned ExtraPredCycles,
369 const BranchProbability &Probability) const{
374 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
376 unsigned ExtraTCycles,
377 MachineBasicBlock &FMBB,
379 unsigned ExtraFCycles,
380 const BranchProbability &Probability) const {
385 R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
387 const BranchProbability &Probability)
393 R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
394 MachineBasicBlock &FMBB) const {
400 R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
401 MachineOperand &MO = Cond[1];
402 switch (MO.getImm()) {
403 case OPCODE_IS_ZERO_INT:
404 MO.setImm(OPCODE_IS_NOT_ZERO_INT);
406 case OPCODE_IS_NOT_ZERO_INT:
407 MO.setImm(OPCODE_IS_ZERO_INT);
410 MO.setImm(OPCODE_IS_NOT_ZERO);
412 case OPCODE_IS_NOT_ZERO:
413 MO.setImm(OPCODE_IS_ZERO);
419 MachineOperand &MO2 = Cond[2];
420 switch (MO2.getReg()) {
421 case AMDGPU::PRED_SEL_ZERO:
422 MO2.setReg(AMDGPU::PRED_SEL_ONE);
424 case AMDGPU::PRED_SEL_ONE:
425 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
434 R600InstrInfo::DefinesPredicate(MachineInstr *MI,
435 std::vector<MachineOperand> &Pred) const {
436 return isPredicateSetter(MI->getOpcode());
441 R600InstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
442 const SmallVectorImpl<MachineOperand> &Pred2) const {
448 R600InstrInfo::PredicateInstruction(MachineInstr *MI,
449 const SmallVectorImpl<MachineOperand> &Pred) const {
450 int PIdx = MI->findFirstPredOperandIdx();
453 MachineOperand &PMO = MI->getOperand(PIdx);
454 PMO.setReg(Pred[2].getReg());
455 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
456 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
463 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
464 const MachineInstr *MI,
465 unsigned *PredCost) const {
471 int R600InstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
472 const MachineRegisterInfo &MRI = MF.getRegInfo();
473 const MachineFrameInfo *MFI = MF.getFrameInfo();
476 if (MFI->getNumObjects() == 0) {
480 if (MRI.livein_empty()) {
484 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
485 LE = MRI.livein_end();
487 Offset = std::max(Offset,
488 GET_REG_INDEX(RI.getEncodingValue(LI->first)));
494 int R600InstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
496 const MachineFrameInfo *MFI = MF.getFrameInfo();
498 // Variable sized objects are not supported
499 assert(!MFI->hasVarSizedObjects());
501 if (MFI->getNumObjects() == 0) {
505 Offset = TM.getFrameLowering()->getFrameIndexOffset(MF, -1);
507 return getIndirectIndexBegin(MF) + Offset;
510 std::vector<unsigned> R600InstrInfo::getIndirectReservedRegs(
511 const MachineFunction &MF) const {
512 const AMDGPUFrameLowering *TFL =
513 static_cast<const AMDGPUFrameLowering*>(TM.getFrameLowering());
514 std::vector<unsigned> Regs;
516 unsigned StackWidth = TFL->getStackWidth(MF);
517 int End = getIndirectIndexEnd(MF);
523 for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
524 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
525 Regs.push_back(SuperReg);
526 for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
527 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
534 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex,
535 unsigned Channel) const {
536 // XXX: Remove when we support a stack width > 2
537 assert(Channel == 0);
541 const TargetRegisterClass * R600InstrInfo::getIndirectAddrStoreRegClass(
542 unsigned SourceReg) const {
543 return &AMDGPU::R600_TReg32RegClass;
546 const TargetRegisterClass *R600InstrInfo::getIndirectAddrLoadRegClass() const {
547 return &AMDGPU::TRegMemRegClass;
550 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
551 MachineBasicBlock::iterator I,
552 unsigned ValueReg, unsigned Address,
553 unsigned OffsetReg) const {
554 unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
555 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
556 AMDGPU::AR_X, OffsetReg);
557 setImmOperand(MOVA, R600Operands::WRITE, 0);
559 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
561 .addReg(AMDGPU::AR_X, RegState::Implicit);
562 setImmOperand(Mov, R600Operands::DST_REL, 1);
566 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
567 MachineBasicBlock::iterator I,
568 unsigned ValueReg, unsigned Address,
569 unsigned OffsetReg) const {
570 unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
571 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
574 setImmOperand(MOVA, R600Operands::WRITE, 0);
575 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
578 .addReg(AMDGPU::AR_X, RegState::Implicit);
579 setImmOperand(Mov, R600Operands::SRC0_REL, 1);
584 const TargetRegisterClass *R600InstrInfo::getSuperIndirectRegClass() const {
585 return &AMDGPU::IndirectRegRegClass;
589 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
590 MachineBasicBlock::iterator I,
594 unsigned Src1Reg) const {
595 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
599 MIB.addImm(0) // $update_exec_mask
600 .addImm(0); // $update_predicate
602 MIB.addImm(1) // $write
604 .addImm(0) // $dst_rel
605 .addImm(0) // $dst_clamp
606 .addReg(Src0Reg) // $src0
607 .addImm(0) // $src0_neg
608 .addImm(0) // $src0_rel
609 .addImm(0) // $src0_abs
610 .addImm(-1); // $src0_sel
613 MIB.addReg(Src1Reg) // $src1
614 .addImm(0) // $src1_neg
615 .addImm(0) // $src1_rel
616 .addImm(0) // $src1_abs
617 .addImm(-1); // $src1_sel
620 //XXX: The r600g finalizer expects this to be 1, once we've moved the
621 //scheduling to the backend, we can change the default to 0.
622 MIB.addImm(1) // $last
623 .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
624 .addImm(0); // $literal
629 MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
630 MachineBasicBlock::iterator I,
632 uint64_t Imm) const {
633 MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
634 AMDGPU::ALU_LITERAL_X);
635 setImmOperand(MovImm, R600Operands::IMM, Imm);
639 int R600InstrInfo::getOperandIdx(const MachineInstr &MI,
640 R600Operands::Ops Op) const {
641 return getOperandIdx(MI.getOpcode(), Op);
644 int R600InstrInfo::getOperandIdx(unsigned Opcode,
645 R600Operands::Ops Op) const {
646 unsigned TargetFlags = get(Opcode).TSFlags;
649 if (!HAS_NATIVE_OPERANDS(TargetFlags)) {
651 case R600Operands::DST: return 0;
652 case R600Operands::SRC0: return 1;
653 case R600Operands::SRC1: return 2;
654 case R600Operands::SRC2: return 3;
656 assert(!"Unknown operand type for instruction");
661 if (TargetFlags & R600_InstFlag::OP1) {
663 } else if (TargetFlags & R600_InstFlag::OP2) {
666 assert((TargetFlags & R600_InstFlag::OP3) && "OP1, OP2, or OP3 not defined "
667 "for this instruction");
671 return R600Operands::ALUOpTable[OpTableIdx][Op];
674 void R600InstrInfo::setImmOperand(MachineInstr *MI, R600Operands::Ops Op,
676 int Idx = getOperandIdx(*MI, Op);
677 assert(Idx != -1 && "Operand not supported for this instruction.");
678 assert(MI->getOperand(Idx).isImm());
679 MI->getOperand(Idx).setImm(Imm);
682 //===----------------------------------------------------------------------===//
683 // Instruction flag getters/setters
684 //===----------------------------------------------------------------------===//
686 bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const {
687 return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
690 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr *MI, unsigned SrcIdx,
691 unsigned Flag) const {
692 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
695 // If we pass something other than the default value of Flag to this
696 // function, it means we are want to set a flag on an instruction
697 // that uses native encoding.
698 assert(HAS_NATIVE_OPERANDS(TargetFlags));
699 bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3;
702 FlagIndex = getOperandIdx(*MI, R600Operands::CLAMP);
705 FlagIndex = getOperandIdx(*MI, R600Operands::WRITE);
707 case MO_FLAG_NOT_LAST:
709 FlagIndex = getOperandIdx(*MI, R600Operands::LAST);
713 case 0: FlagIndex = getOperandIdx(*MI, R600Operands::SRC0_NEG); break;
714 case 1: FlagIndex = getOperandIdx(*MI, R600Operands::SRC1_NEG); break;
715 case 2: FlagIndex = getOperandIdx(*MI, R600Operands::SRC2_NEG); break;
720 assert(!IsOP3 && "Cannot set absolute value modifier for OP3 "
724 case 0: FlagIndex = getOperandIdx(*MI, R600Operands::SRC0_ABS); break;
725 case 1: FlagIndex = getOperandIdx(*MI, R600Operands::SRC1_ABS); break;
733 assert(FlagIndex != -1 && "Flag not supported for this instruction");
735 FlagIndex = GET_FLAG_OPERAND_IDX(TargetFlags);
736 assert(FlagIndex != 0 &&
737 "Instruction flags not supported for this instruction");
740 MachineOperand &FlagOp = MI->getOperand(FlagIndex);
741 assert(FlagOp.isImm());
745 void R600InstrInfo::addFlag(MachineInstr *MI, unsigned Operand,
746 unsigned Flag) const {
747 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
751 if (HAS_NATIVE_OPERANDS(TargetFlags)) {
752 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
753 if (Flag == MO_FLAG_NOT_LAST) {
754 clearFlag(MI, Operand, MO_FLAG_LAST);
755 } else if (Flag == MO_FLAG_MASK) {
756 clearFlag(MI, Operand, Flag);
761 MachineOperand &FlagOp = getFlagOp(MI, Operand);
762 FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
766 void R600InstrInfo::clearFlag(MachineInstr *MI, unsigned Operand,
767 unsigned Flag) const {
768 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
769 if (HAS_NATIVE_OPERANDS(TargetFlags)) {
770 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
773 MachineOperand &FlagOp = getFlagOp(MI);
774 unsigned InstFlags = FlagOp.getImm();
775 InstFlags &= ~(Flag << (NUM_MO_FLAGS * Operand));
776 FlagOp.setImm(InstFlags);