1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for R600
13 //===----------------------------------------------------------------------===//
15 #include "R600ISelLowering.h"
16 #include "AMDGPUFrameLowering.h"
17 #include "AMDGPUIntrinsicInfo.h"
18 #include "AMDGPUSubtarget.h"
19 #include "R600Defines.h"
20 #include "R600InstrInfo.h"
21 #include "R600MachineFunctionInfo.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/IR/Argument.h"
28 #include "llvm/IR/Function.h"
32 R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
33 AMDGPUTargetLowering(TM),
34 Gen(TM.getSubtarget<AMDGPUSubtarget>().getGeneration()) {
35 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
36 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
37 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
38 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
39 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
40 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
42 computeRegisterProperties();
44 // Set condition code actions
45 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
46 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
47 setCondCodeAction(ISD::SETLT, MVT::f32, Expand);
48 setCondCodeAction(ISD::SETLE, MVT::f32, Expand);
49 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
50 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
51 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
52 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
53 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
54 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
55 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
56 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
58 setCondCodeAction(ISD::SETLE, MVT::i32, Expand);
59 setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
60 setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
61 setCondCodeAction(ISD::SETULT, MVT::i32, Expand);
63 setOperationAction(ISD::FCOS, MVT::f32, Custom);
64 setOperationAction(ISD::FSIN, MVT::f32, Custom);
66 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
67 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
69 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
70 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
72 setOperationAction(ISD::FSUB, MVT::f32, Expand);
74 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
75 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
76 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
78 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
79 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
81 setOperationAction(ISD::SETCC, MVT::i32, Expand);
82 setOperationAction(ISD::SETCC, MVT::f32, Expand);
83 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
85 setOperationAction(ISD::SELECT, MVT::i32, Expand);
86 setOperationAction(ISD::SELECT, MVT::f32, Expand);
87 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
88 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
90 // Expand sign extension of vectors
91 if (!Subtarget->hasBFE())
92 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
94 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand);
95 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand);
97 if (!Subtarget->hasBFE())
98 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
99 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand);
100 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand);
102 if (!Subtarget->hasBFE())
103 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
104 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand);
105 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand);
109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
111 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
114 // Legalize loads and stores to the private address space.
115 setOperationAction(ISD::LOAD, MVT::i32, Custom);
116 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
117 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
119 // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address
120 // spaces, so it is custom lowered to handle those where it isn't.
121 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
122 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
123 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
125 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
126 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Custom);
128 setOperationAction(ISD::STORE, MVT::i8, Custom);
129 setOperationAction(ISD::STORE, MVT::i32, Custom);
130 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
131 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
132 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
133 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
135 setOperationAction(ISD::LOAD, MVT::i32, Custom);
136 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
137 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom);
140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom);
141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
144 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom);
145 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom);
146 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
149 setTargetDAGCombine(ISD::FP_ROUND);
150 setTargetDAGCombine(ISD::FP_TO_SINT);
151 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
152 setTargetDAGCombine(ISD::SELECT_CC);
153 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
155 // These should be replaced by UDVIREM, but it does not happen automatically
156 // during Type Legalization
157 setOperationAction(ISD::UDIV, MVT::i64, Custom);
158 setOperationAction(ISD::UREM, MVT::i64, Custom);
159 setOperationAction(ISD::SDIV, MVT::i64, Custom);
160 setOperationAction(ISD::SREM, MVT::i64, Custom);
162 // We don't have 64-bit shifts. Thus we need either SHX i64 or SHX_PARTS i32
163 // to be Legal/Custom in order to avoid library calls.
164 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
165 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
166 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
168 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
170 setBooleanContents(ZeroOrNegativeOneBooleanContent);
171 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
172 setSchedulingPreference(Sched::Source);
175 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
176 MachineInstr * MI, MachineBasicBlock * BB) const {
177 MachineFunction * MF = BB->getParent();
178 MachineRegisterInfo &MRI = MF->getRegInfo();
179 MachineBasicBlock::iterator I = *MI;
180 const R600InstrInfo *TII =
181 static_cast<const R600InstrInfo*>(MF->getTarget().getInstrInfo());
183 switch (MI->getOpcode()) {
185 // Replace LDS_*_RET instruction that don't have any uses with the
186 // equivalent LDS_*_NORET instruction.
187 if (TII->isLDSRetInstr(MI->getOpcode())) {
188 int DstIdx = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
189 assert(DstIdx != -1);
190 MachineInstrBuilder NewMI;
191 if (!MRI.use_empty(MI->getOperand(DstIdx).getReg()))
194 NewMI = BuildMI(*BB, I, BB->findDebugLoc(I),
195 TII->get(AMDGPU::getLDSNoRetOp(MI->getOpcode())));
196 for (unsigned i = 1, e = MI->getNumOperands(); i < e; ++i) {
197 NewMI.addOperand(MI->getOperand(i));
200 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
203 case AMDGPU::CLAMP_R600: {
204 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
206 MI->getOperand(0).getReg(),
207 MI->getOperand(1).getReg());
208 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
212 case AMDGPU::FABS_R600: {
213 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
215 MI->getOperand(0).getReg(),
216 MI->getOperand(1).getReg());
217 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
221 case AMDGPU::FNEG_R600: {
222 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
224 MI->getOperand(0).getReg(),
225 MI->getOperand(1).getReg());
226 TII->addFlag(NewMI, 0, MO_FLAG_NEG);
230 case AMDGPU::MASK_WRITE: {
231 unsigned maskedRegister = MI->getOperand(0).getReg();
232 assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
233 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
234 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
238 case AMDGPU::MOV_IMM_F32:
239 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
240 MI->getOperand(1).getFPImm()->getValueAPF()
241 .bitcastToAPInt().getZExtValue());
243 case AMDGPU::MOV_IMM_I32:
244 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
245 MI->getOperand(1).getImm());
247 case AMDGPU::CONST_COPY: {
248 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
249 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
250 TII->setImmOperand(NewMI, AMDGPU::OpName::src0_sel,
251 MI->getOperand(1).getImm());
255 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
256 case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
257 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
258 unsigned EOP = (std::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
260 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
261 .addOperand(MI->getOperand(0))
262 .addOperand(MI->getOperand(1))
263 .addImm(EOP); // Set End of program bit
268 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
269 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
270 MachineOperand &RID = MI->getOperand(4);
271 MachineOperand &SID = MI->getOperand(5);
272 unsigned TextureId = MI->getOperand(6).getImm();
273 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
274 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
286 case 8: // ShadowRect
297 case 11: // Shadow1DArray
301 case 12: // Shadow2DArray
305 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
306 .addOperand(MI->getOperand(3))
324 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
325 .addOperand(MI->getOperand(2))
343 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
344 .addOperand(MI->getOperand(0))
345 .addOperand(MI->getOperand(1))
363 .addReg(T0, RegState::Implicit)
364 .addReg(T1, RegState::Implicit);
368 case AMDGPU::TXD_SHADOW: {
369 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
370 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
371 MachineOperand &RID = MI->getOperand(4);
372 MachineOperand &SID = MI->getOperand(5);
373 unsigned TextureId = MI->getOperand(6).getImm();
374 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
375 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
387 case 8: // ShadowRect
398 case 11: // Shadow1DArray
402 case 12: // Shadow2DArray
407 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
408 .addOperand(MI->getOperand(3))
426 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
427 .addOperand(MI->getOperand(2))
445 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
446 .addOperand(MI->getOperand(0))
447 .addOperand(MI->getOperand(1))
465 .addReg(T0, RegState::Implicit)
466 .addReg(T1, RegState::Implicit);
471 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
472 .addOperand(MI->getOperand(0));
475 case AMDGPU::BRANCH_COND_f32: {
476 MachineInstr *NewMI =
477 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
478 AMDGPU::PREDICATE_BIT)
479 .addOperand(MI->getOperand(1))
480 .addImm(OPCODE_IS_NOT_ZERO)
482 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
483 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
484 .addOperand(MI->getOperand(0))
485 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
489 case AMDGPU::BRANCH_COND_i32: {
490 MachineInstr *NewMI =
491 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
492 AMDGPU::PREDICATE_BIT)
493 .addOperand(MI->getOperand(1))
494 .addImm(OPCODE_IS_NOT_ZERO_INT)
496 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
497 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
498 .addOperand(MI->getOperand(0))
499 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
503 case AMDGPU::EG_ExportSwz:
504 case AMDGPU::R600_ExportSwz: {
505 // Instruction is left unmodified if its not the last one of its type
506 bool isLastInstructionOfItsType = true;
507 unsigned InstExportType = MI->getOperand(1).getImm();
508 for (MachineBasicBlock::iterator NextExportInst = std::next(I),
509 EndBlock = BB->end(); NextExportInst != EndBlock;
510 NextExportInst = std::next(NextExportInst)) {
511 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
512 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
513 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
515 if (CurrentInstExportType == InstExportType) {
516 isLastInstructionOfItsType = false;
521 bool EOP = (std::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
522 if (!EOP && !isLastInstructionOfItsType)
524 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
525 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
526 .addOperand(MI->getOperand(0))
527 .addOperand(MI->getOperand(1))
528 .addOperand(MI->getOperand(2))
529 .addOperand(MI->getOperand(3))
530 .addOperand(MI->getOperand(4))
531 .addOperand(MI->getOperand(5))
532 .addOperand(MI->getOperand(6))
537 case AMDGPU::RETURN: {
538 // RETURN instructions must have the live-out registers as implicit uses,
539 // otherwise they appear dead.
540 R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
541 MachineInstrBuilder MIB(*MF, MI);
542 for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
543 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
548 MI->eraseFromParent();
552 //===----------------------------------------------------------------------===//
553 // Custom DAG Lowering Operations
554 //===----------------------------------------------------------------------===//
556 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
557 MachineFunction &MF = DAG.getMachineFunction();
558 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
559 switch (Op.getOpcode()) {
560 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
561 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
562 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
563 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
565 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
567 case ISD::FSIN: return LowerTrig(Op, DAG);
568 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
569 case ISD::STORE: return LowerSTORE(Op, DAG);
570 case ISD::LOAD: return LowerLOAD(Op, DAG);
571 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
572 case ISD::INTRINSIC_VOID: {
573 SDValue Chain = Op.getOperand(0);
574 unsigned IntrinsicID =
575 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
576 switch (IntrinsicID) {
577 case AMDGPUIntrinsic::AMDGPU_store_output: {
578 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
579 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
580 MFI->LiveOuts.push_back(Reg);
581 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
583 case AMDGPUIntrinsic::R600_store_swizzle: {
584 const SDValue Args[8] = {
586 Op.getOperand(2), // Export Value
587 Op.getOperand(3), // ArrayBase
588 Op.getOperand(4), // Type
589 DAG.getConstant(0, MVT::i32), // SWZ_X
590 DAG.getConstant(1, MVT::i32), // SWZ_Y
591 DAG.getConstant(2, MVT::i32), // SWZ_Z
592 DAG.getConstant(3, MVT::i32) // SWZ_W
594 return DAG.getNode(AMDGPUISD::EXPORT, SDLoc(Op), Op.getValueType(), Args);
597 // default for switch(IntrinsicID)
600 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
603 case ISD::INTRINSIC_WO_CHAIN: {
604 unsigned IntrinsicID =
605 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
606 EVT VT = Op.getValueType();
608 switch(IntrinsicID) {
609 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
610 case AMDGPUIntrinsic::R600_load_input: {
611 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
612 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
613 MachineFunction &MF = DAG.getMachineFunction();
614 MachineRegisterInfo &MRI = MF.getRegInfo();
616 return DAG.getCopyFromReg(DAG.getEntryNode(),
617 SDLoc(DAG.getEntryNode()), Reg, VT);
620 case AMDGPUIntrinsic::R600_interp_input: {
621 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
622 int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
623 MachineSDNode *interp;
625 const MachineFunction &MF = DAG.getMachineFunction();
626 const R600InstrInfo *TII =
627 static_cast<const R600InstrInfo*>(MF.getTarget().getInstrInfo());
628 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
629 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
630 return DAG.getTargetExtractSubreg(
631 TII->getRegisterInfo().getSubRegFromChannel(slot % 4),
632 DL, MVT::f32, SDValue(interp, 0));
634 MachineFunction &MF = DAG.getMachineFunction();
635 MachineRegisterInfo &MRI = MF.getRegInfo();
636 unsigned RegisterI = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb);
637 unsigned RegisterJ = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1);
638 MRI.addLiveIn(RegisterI);
639 MRI.addLiveIn(RegisterJ);
640 SDValue RegisterINode = DAG.getCopyFromReg(DAG.getEntryNode(),
641 SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32);
642 SDValue RegisterJNode = DAG.getCopyFromReg(DAG.getEntryNode(),
643 SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32);
646 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
647 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
648 RegisterJNode, RegisterINode);
650 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
651 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
652 RegisterJNode, RegisterINode);
653 return SDValue(interp, slot % 2);
655 case AMDGPUIntrinsic::R600_interp_xy:
656 case AMDGPUIntrinsic::R600_interp_zw: {
657 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
658 MachineSDNode *interp;
659 SDValue RegisterINode = Op.getOperand(2);
660 SDValue RegisterJNode = Op.getOperand(3);
662 if (IntrinsicID == AMDGPUIntrinsic::R600_interp_xy)
663 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
664 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, MVT::i32),
665 RegisterJNode, RegisterINode);
667 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
668 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, MVT::i32),
669 RegisterJNode, RegisterINode);
670 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32,
671 SDValue(interp, 0), SDValue(interp, 1));
673 case AMDGPUIntrinsic::R600_tex:
674 case AMDGPUIntrinsic::R600_texc:
675 case AMDGPUIntrinsic::R600_txl:
676 case AMDGPUIntrinsic::R600_txlc:
677 case AMDGPUIntrinsic::R600_txb:
678 case AMDGPUIntrinsic::R600_txbc:
679 case AMDGPUIntrinsic::R600_txf:
680 case AMDGPUIntrinsic::R600_txq:
681 case AMDGPUIntrinsic::R600_ddx:
682 case AMDGPUIntrinsic::R600_ddy:
683 case AMDGPUIntrinsic::R600_ldptr: {
685 switch (IntrinsicID) {
686 case AMDGPUIntrinsic::R600_tex:
689 case AMDGPUIntrinsic::R600_texc:
692 case AMDGPUIntrinsic::R600_txl:
695 case AMDGPUIntrinsic::R600_txlc:
698 case AMDGPUIntrinsic::R600_txb:
701 case AMDGPUIntrinsic::R600_txbc:
704 case AMDGPUIntrinsic::R600_txf:
707 case AMDGPUIntrinsic::R600_txq:
710 case AMDGPUIntrinsic::R600_ddx:
713 case AMDGPUIntrinsic::R600_ddy:
716 case AMDGPUIntrinsic::R600_ldptr:
720 llvm_unreachable("Unknow Texture Operation");
723 SDValue TexArgs[19] = {
724 DAG.getConstant(TextureOp, MVT::i32),
726 DAG.getConstant(0, MVT::i32),
727 DAG.getConstant(1, MVT::i32),
728 DAG.getConstant(2, MVT::i32),
729 DAG.getConstant(3, MVT::i32),
733 DAG.getConstant(0, MVT::i32),
734 DAG.getConstant(1, MVT::i32),
735 DAG.getConstant(2, MVT::i32),
736 DAG.getConstant(3, MVT::i32),
744 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
746 case AMDGPUIntrinsic::AMDGPU_dp4: {
748 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
749 DAG.getConstant(0, MVT::i32)),
750 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
751 DAG.getConstant(0, MVT::i32)),
752 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
753 DAG.getConstant(1, MVT::i32)),
754 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
755 DAG.getConstant(1, MVT::i32)),
756 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
757 DAG.getConstant(2, MVT::i32)),
758 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
759 DAG.getConstant(2, MVT::i32)),
760 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
761 DAG.getConstant(3, MVT::i32)),
762 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
763 DAG.getConstant(3, MVT::i32))
765 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args);
768 case Intrinsic::r600_read_ngroups_x:
769 return LowerImplicitParameter(DAG, VT, DL, 0);
770 case Intrinsic::r600_read_ngroups_y:
771 return LowerImplicitParameter(DAG, VT, DL, 1);
772 case Intrinsic::r600_read_ngroups_z:
773 return LowerImplicitParameter(DAG, VT, DL, 2);
774 case Intrinsic::r600_read_global_size_x:
775 return LowerImplicitParameter(DAG, VT, DL, 3);
776 case Intrinsic::r600_read_global_size_y:
777 return LowerImplicitParameter(DAG, VT, DL, 4);
778 case Intrinsic::r600_read_global_size_z:
779 return LowerImplicitParameter(DAG, VT, DL, 5);
780 case Intrinsic::r600_read_local_size_x:
781 return LowerImplicitParameter(DAG, VT, DL, 6);
782 case Intrinsic::r600_read_local_size_y:
783 return LowerImplicitParameter(DAG, VT, DL, 7);
784 case Intrinsic::r600_read_local_size_z:
785 return LowerImplicitParameter(DAG, VT, DL, 8);
787 case Intrinsic::r600_read_tgid_x:
788 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
790 case Intrinsic::r600_read_tgid_y:
791 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
793 case Intrinsic::r600_read_tgid_z:
794 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
796 case Intrinsic::r600_read_tidig_x:
797 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
799 case Intrinsic::r600_read_tidig_y:
800 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
802 case Intrinsic::r600_read_tidig_z:
803 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
806 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
809 } // end switch(Op.getOpcode())
813 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
814 SmallVectorImpl<SDValue> &Results,
815 SelectionDAG &DAG) const {
816 switch (N->getOpcode()) {
818 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG);
820 case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
823 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
824 Results.push_back(SDValue(Node, 0));
825 Results.push_back(SDValue(Node, 1));
826 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
828 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
832 SDNode *Node = LowerSTORE(SDValue(N, 0), DAG).getNode();
833 Results.push_back(SDValue(Node, 0));
837 SDValue Op = SDValue(N, 0);
839 EVT VT = Op.getValueType();
840 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
841 N->getOperand(0), N->getOperand(1));
842 Results.push_back(UDIVREM);
846 SDValue Op = SDValue(N, 0);
848 EVT VT = Op.getValueType();
849 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
850 N->getOperand(0), N->getOperand(1));
851 Results.push_back(UDIVREM.getValue(1));
855 SDValue Op = SDValue(N, 0);
857 EVT VT = Op.getValueType();
858 SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT),
859 N->getOperand(0), N->getOperand(1));
860 Results.push_back(SDIVREM);
864 SDValue Op = SDValue(N, 0);
866 EVT VT = Op.getValueType();
867 SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT),
868 N->getOperand(0), N->getOperand(1));
869 Results.push_back(SDIVREM.getValue(1));
873 SDValue Op = SDValue(N, 1);
874 SDValue RES = LowerSDIVREM(Op, DAG);
875 Results.push_back(RES);
876 Results.push_back(RES.getValue(1));
880 SDValue Op = SDValue(N, 0);
882 EVT VT = Op.getValueType();
883 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
885 SDValue one = DAG.getConstant(1, HalfVT);
886 SDValue zero = DAG.getConstant(0, HalfVT);
889 SDValue LHS = N->getOperand(0);
890 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
891 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
893 SDValue RHS = N->getOperand(1);
894 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
895 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
897 // Get Speculative values
898 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
899 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
901 SDValue REM_Hi = zero;
902 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
904 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
905 SDValue DIV_Lo = zero;
907 const unsigned halfBitWidth = HalfVT.getSizeInBits();
909 for (unsigned i = 0; i < halfBitWidth; ++i) {
910 SDValue POS = DAG.getConstant(halfBitWidth - i - 1, HalfVT);
911 // Get Value of high bit
913 if (halfBitWidth == 32 && Subtarget->hasBFE()) {
914 HBit = DAG.getNode(AMDGPUISD::BFE_U32, DL, HalfVT, LHS_Lo, POS, one);
916 HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
917 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
920 SDValue Carry = DAG.getNode(ISD::SRL, DL, HalfVT, REM_Lo,
921 DAG.getConstant(halfBitWidth - 1, HalfVT));
922 REM_Hi = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Hi, one);
923 REM_Hi = DAG.getNode(ISD::OR, DL, HalfVT, REM_Hi, Carry);
925 REM_Lo = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Lo, one);
926 REM_Lo = DAG.getNode(ISD::OR, DL, HalfVT, REM_Lo, HBit);
929 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
931 SDValue BIT = DAG.getConstant(1 << (halfBitWidth - i - 1), HalfVT);
932 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETGE);
934 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
938 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
940 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETGE);
941 REM_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, zero);
942 REM_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, one);
945 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
946 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
947 Results.push_back(DIV);
948 Results.push_back(REM);
954 SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG,
955 SDValue Vector) const {
958 EVT VecVT = Vector.getValueType();
959 EVT EltVT = VecVT.getVectorElementType();
960 SmallVector<SDValue, 8> Args;
962 for (unsigned i = 0, e = VecVT.getVectorNumElements();
964 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
965 Vector, DAG.getConstant(i, getVectorIdxTy())));
968 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args);
971 SDValue R600TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
972 SelectionDAG &DAG) const {
975 SDValue Vector = Op.getOperand(0);
976 SDValue Index = Op.getOperand(1);
978 if (isa<ConstantSDNode>(Index) ||
979 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
982 Vector = vectorToVerticalVector(DAG, Vector);
983 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(),
987 SDValue R600TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
988 SelectionDAG &DAG) const {
990 SDValue Vector = Op.getOperand(0);
991 SDValue Value = Op.getOperand(1);
992 SDValue Index = Op.getOperand(2);
994 if (isa<ConstantSDNode>(Index) ||
995 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
998 Vector = vectorToVerticalVector(DAG, Vector);
999 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(),
1000 Vector, Value, Index);
1001 return vectorToVerticalVector(DAG, Insert);
1004 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
1005 // On hw >= R700, COS/SIN input must be between -1. and 1.
1006 // Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
1007 EVT VT = Op.getValueType();
1008 SDValue Arg = Op.getOperand(0);
1009 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
1010 DAG.getNode(ISD::FADD, SDLoc(Op), VT,
1011 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
1012 DAG.getConstantFP(0.15915494309, MVT::f32)),
1013 DAG.getConstantFP(0.5, MVT::f32)));
1015 switch (Op.getOpcode()) {
1017 TrigNode = AMDGPUISD::COS_HW;
1020 TrigNode = AMDGPUISD::SIN_HW;
1023 llvm_unreachable("Wrong trig opcode");
1025 SDValue TrigVal = DAG.getNode(TrigNode, SDLoc(Op), VT,
1026 DAG.getNode(ISD::FADD, SDLoc(Op), VT, FractPart,
1027 DAG.getConstantFP(-0.5, MVT::f32)));
1028 if (Gen >= AMDGPUSubtarget::R700)
1030 // On R600 hw, COS/SIN input must be between -Pi and Pi.
1031 return DAG.getNode(ISD::FMUL, SDLoc(Op), VT, TrigVal,
1032 DAG.getConstantFP(3.14159265359, MVT::f32));
1035 SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const {
1037 EVT VT = Op.getValueType();
1039 SDValue Lo = Op.getOperand(0);
1040 SDValue Hi = Op.getOperand(1);
1041 SDValue Shift = Op.getOperand(2);
1042 SDValue Zero = DAG.getConstant(0, VT);
1043 SDValue One = DAG.getConstant(1, VT);
1045 SDValue Width = DAG.getConstant(VT.getSizeInBits(), VT);
1046 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, VT);
1047 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
1048 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
1050 // The dance around Width1 is necessary for 0 special case.
1051 // Without it the CompShift might be 32, producing incorrect results in
1052 // Overflow. So we do the shift in two steps, the alternative is to
1053 // add a conditional to filter the special case.
1055 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift);
1056 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One);
1058 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift);
1059 HiSmall = DAG.getNode(ISD::OR, DL, VT, HiSmall, Overflow);
1060 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift);
1062 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift);
1063 SDValue LoBig = Zero;
1065 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
1066 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
1068 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
1071 SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const {
1073 EVT VT = Op.getValueType();
1075 SDValue Lo = Op.getOperand(0);
1076 SDValue Hi = Op.getOperand(1);
1077 SDValue Shift = Op.getOperand(2);
1078 SDValue Zero = DAG.getConstant(0, VT);
1079 SDValue One = DAG.getConstant(1, VT);
1081 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS;
1083 SDValue Width = DAG.getConstant(VT.getSizeInBits(), VT);
1084 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, VT);
1085 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
1086 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
1088 // The dance around Width1 is necessary for 0 special case.
1089 // Without it the CompShift might be 32, producing incorrect results in
1090 // Overflow. So we do the shift in two steps, the alternative is to
1091 // add a conditional to filter the special case.
1093 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift);
1094 Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One);
1096 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift);
1097 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift);
1098 LoSmall = DAG.getNode(ISD::OR, DL, VT, LoSmall, Overflow);
1100 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift);
1101 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero;
1103 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
1104 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
1106 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
1109 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
1114 Op, DAG.getConstantFP(0.0f, MVT::f32),
1115 DAG.getCondCode(ISD::SETNE)
1119 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
1121 unsigned DwordOffset) const {
1122 unsigned ByteOffset = DwordOffset * 4;
1123 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1124 AMDGPUAS::CONSTANT_BUFFER_0);
1126 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
1127 assert(isInt<16>(ByteOffset));
1129 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
1130 DAG.getConstant(ByteOffset, MVT::i32), // PTR
1131 MachinePointerInfo(ConstantPointerNull::get(PtrType)),
1132 false, false, false, 0);
1135 bool R600TargetLowering::isZero(SDValue Op) const {
1136 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
1137 return Cst->isNullValue();
1138 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
1139 return CstFP->isZero();
1145 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
1147 EVT VT = Op.getValueType();
1149 SDValue LHS = Op.getOperand(0);
1150 SDValue RHS = Op.getOperand(1);
1151 SDValue True = Op.getOperand(2);
1152 SDValue False = Op.getOperand(3);
1153 SDValue CC = Op.getOperand(4);
1156 // LHS and RHS are guaranteed to be the same value type
1157 EVT CompareVT = LHS.getValueType();
1159 // Check if we can lower this to a native operation.
1161 // Try to lower to a SET* instruction:
1163 // SET* can match the following patterns:
1165 // select_cc f32, f32, -1, 0, cc_supported
1166 // select_cc f32, f32, 1.0f, 0.0f, cc_supported
1167 // select_cc i32, i32, -1, 0, cc_supported
1170 // Move hardware True/False values to the correct operand.
1171 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1172 ISD::CondCode InverseCC =
1173 ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
1174 if (isHWTrueValue(False) && isHWFalseValue(True)) {
1175 if (isCondCodeLegal(InverseCC, CompareVT.getSimpleVT())) {
1176 std::swap(False, True);
1177 CC = DAG.getCondCode(InverseCC);
1179 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InverseCC);
1180 if (isCondCodeLegal(SwapInvCC, CompareVT.getSimpleVT())) {
1181 std::swap(False, True);
1182 std::swap(LHS, RHS);
1183 CC = DAG.getCondCode(SwapInvCC);
1188 if (isHWTrueValue(True) && isHWFalseValue(False) &&
1189 (CompareVT == VT || VT == MVT::i32)) {
1190 // This can be matched by a SET* instruction.
1191 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
1194 // Try to lower to a CND* instruction:
1196 // CND* can match the following patterns:
1198 // select_cc f32, 0.0, f32, f32, cc_supported
1199 // select_cc f32, 0.0, i32, i32, cc_supported
1200 // select_cc i32, 0, f32, f32, cc_supported
1201 // select_cc i32, 0, i32, i32, cc_supported
1204 // Try to move the zero value to the RHS
1206 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1207 // Try swapping the operands
1208 ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(CCOpcode);
1209 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
1210 std::swap(LHS, RHS);
1211 CC = DAG.getCondCode(CCSwapped);
1213 // Try inverting the conditon and then swapping the operands
1214 ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT.isInteger());
1215 CCSwapped = ISD::getSetCCSwappedOperands(CCInv);
1216 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
1217 std::swap(True, False);
1218 std::swap(LHS, RHS);
1219 CC = DAG.getCondCode(CCSwapped);
1226 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1227 if (CompareVT != VT) {
1228 // Bitcast True / False to the correct types. This will end up being
1229 // a nop, but it allows us to define only a single pattern in the
1230 // .TD files for each CND* instruction rather than having to have
1231 // one pattern for integer True/False and one for fp True/False
1232 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
1233 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
1240 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
1248 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
1251 DAG.getCondCode(CCOpcode));
1252 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
1255 // If we make it this for it means we have no native instructions to handle
1256 // this SELECT_CC, so we must lower it.
1257 SDValue HWTrue, HWFalse;
1259 if (CompareVT == MVT::f32) {
1260 HWTrue = DAG.getConstantFP(1.0f, CompareVT);
1261 HWFalse = DAG.getConstantFP(0.0f, CompareVT);
1262 } else if (CompareVT == MVT::i32) {
1263 HWTrue = DAG.getConstant(-1, CompareVT);
1264 HWFalse = DAG.getConstant(0, CompareVT);
1267 llvm_unreachable("Unhandled value type in LowerSELECT_CC");
1270 // Lower this unsupported SELECT_CC into a combination of two supported
1271 // SELECT_CC operations.
1272 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
1274 return DAG.getNode(ISD::SELECT_CC, DL, VT,
1277 DAG.getCondCode(ISD::SETNE));
1280 /// LLVM generates byte-addressed pointers. For indirect addressing, we need to
1281 /// convert these pointers to a register index. Each register holds
1282 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
1283 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
1284 /// for indirect addressing.
1285 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
1286 unsigned StackWidth,
1287 SelectionDAG &DAG) const {
1289 switch(StackWidth) {
1299 default: llvm_unreachable("Invalid stack width");
1302 return DAG.getNode(ISD::SRL, SDLoc(Ptr), Ptr.getValueType(), Ptr,
1303 DAG.getConstant(SRLPad, MVT::i32));
1306 void R600TargetLowering::getStackAddress(unsigned StackWidth,
1309 unsigned &PtrIncr) const {
1310 switch (StackWidth) {
1321 Channel = ElemIdx % 2;
1335 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1337 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
1338 SDValue Chain = Op.getOperand(0);
1339 SDValue Value = Op.getOperand(1);
1340 SDValue Ptr = Op.getOperand(2);
1342 SDValue Result = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1343 if (Result.getNode()) {
1347 if (StoreNode->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS) {
1348 if (StoreNode->isTruncatingStore()) {
1349 EVT VT = Value.getValueType();
1350 assert(VT.bitsLE(MVT::i32));
1351 EVT MemVT = StoreNode->getMemoryVT();
1352 SDValue MaskConstant;
1353 if (MemVT == MVT::i8) {
1354 MaskConstant = DAG.getConstant(0xFF, MVT::i32);
1356 assert(MemVT == MVT::i16);
1357 MaskConstant = DAG.getConstant(0xFFFF, MVT::i32);
1359 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr,
1360 DAG.getConstant(2, MVT::i32));
1361 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, Ptr.getValueType(), Ptr,
1362 DAG.getConstant(0x00000003, VT));
1363 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant);
1364 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
1365 DAG.getConstant(3, VT));
1366 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, Shift);
1367 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, Shift);
1368 // XXX: If we add a 64-bit ZW register class, then we could use a 2 x i32
1372 DAG.getConstant(0, MVT::i32),
1373 DAG.getConstant(0, MVT::i32),
1376 SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src);
1377 SDValue Args[3] = { Chain, Input, DWordAddr };
1378 return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL,
1379 Op->getVTList(), Args, MemVT,
1380 StoreNode->getMemOperand());
1381 } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR &&
1382 Value.getValueType().bitsGE(MVT::i32)) {
1383 // Convert pointer from byte address to dword address.
1384 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
1385 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
1386 Ptr, DAG.getConstant(2, MVT::i32)));
1388 if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
1389 llvm_unreachable("Truncated and indexed stores not supported yet");
1391 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1397 EVT ValueVT = Value.getValueType();
1399 if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1403 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1404 if (Ret.getNode()) {
1407 // Lowering for indirect addressing
1409 const MachineFunction &MF = DAG.getMachineFunction();
1410 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
1411 getTargetMachine().getFrameLowering());
1412 unsigned StackWidth = TFL->getStackWidth(MF);
1414 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1416 if (ValueVT.isVector()) {
1417 unsigned NumElemVT = ValueVT.getVectorNumElements();
1418 EVT ElemVT = ValueVT.getVectorElementType();
1419 SmallVector<SDValue, 4> Stores(NumElemVT);
1421 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1422 "vector width in load");
1424 for (unsigned i = 0; i < NumElemVT; ++i) {
1425 unsigned Channel, PtrIncr;
1426 getStackAddress(StackWidth, i, Channel, PtrIncr);
1427 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1428 DAG.getConstant(PtrIncr, MVT::i32));
1429 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
1430 Value, DAG.getConstant(i, MVT::i32));
1432 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1434 DAG.getTargetConstant(Channel, MVT::i32));
1436 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores);
1438 if (ValueVT == MVT::i8) {
1439 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1441 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
1442 DAG.getTargetConstant(0, MVT::i32)); // Channel
1448 // return (512 + (kc_bank << 12)
1450 ConstantAddressBlock(unsigned AddressSpace) {
1451 switch (AddressSpace) {
1452 case AMDGPUAS::CONSTANT_BUFFER_0:
1454 case AMDGPUAS::CONSTANT_BUFFER_1:
1456 case AMDGPUAS::CONSTANT_BUFFER_2:
1457 return 512 + 4096 * 2;
1458 case AMDGPUAS::CONSTANT_BUFFER_3:
1459 return 512 + 4096 * 3;
1460 case AMDGPUAS::CONSTANT_BUFFER_4:
1461 return 512 + 4096 * 4;
1462 case AMDGPUAS::CONSTANT_BUFFER_5:
1463 return 512 + 4096 * 5;
1464 case AMDGPUAS::CONSTANT_BUFFER_6:
1465 return 512 + 4096 * 6;
1466 case AMDGPUAS::CONSTANT_BUFFER_7:
1467 return 512 + 4096 * 7;
1468 case AMDGPUAS::CONSTANT_BUFFER_8:
1469 return 512 + 4096 * 8;
1470 case AMDGPUAS::CONSTANT_BUFFER_9:
1471 return 512 + 4096 * 9;
1472 case AMDGPUAS::CONSTANT_BUFFER_10:
1473 return 512 + 4096 * 10;
1474 case AMDGPUAS::CONSTANT_BUFFER_11:
1475 return 512 + 4096 * 11;
1476 case AMDGPUAS::CONSTANT_BUFFER_12:
1477 return 512 + 4096 * 12;
1478 case AMDGPUAS::CONSTANT_BUFFER_13:
1479 return 512 + 4096 * 13;
1480 case AMDGPUAS::CONSTANT_BUFFER_14:
1481 return 512 + 4096 * 14;
1482 case AMDGPUAS::CONSTANT_BUFFER_15:
1483 return 512 + 4096 * 15;
1489 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
1491 EVT VT = Op.getValueType();
1493 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1494 SDValue Chain = Op.getOperand(0);
1495 SDValue Ptr = Op.getOperand(1);
1496 SDValue LoweredLoad;
1498 SDValue Ret = AMDGPUTargetLowering::LowerLOAD(Op, DAG);
1499 if (Ret.getNode()) {
1504 return DAG.getMergeValues(Ops, DL);
1508 if (LoadNode->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS && VT.isVector()) {
1509 SDValue MergedValues[2] = {
1510 SplitVectorLoad(Op, DAG),
1513 return DAG.getMergeValues(MergedValues, DL);
1516 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
1517 if (ConstantBlock > -1 &&
1518 ((LoadNode->getExtensionType() == ISD::NON_EXTLOAD) ||
1519 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) {
1521 if (isa<ConstantExpr>(LoadNode->getMemOperand()->getValue()) ||
1522 isa<Constant>(LoadNode->getMemOperand()->getValue()) ||
1523 isa<ConstantSDNode>(Ptr)) {
1525 for (unsigned i = 0; i < 4; i++) {
1526 // We want Const position encoded with the following formula :
1527 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1528 // const_index is Ptr computed by llvm using an alignment of 16.
1529 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1530 // then div by 4 at the ISel step
1531 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1532 DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
1533 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1535 EVT NewVT = MVT::v4i32;
1536 unsigned NumElements = 4;
1537 if (VT.isVector()) {
1539 NumElements = VT.getVectorNumElements();
1541 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT,
1542 makeArrayRef(Slots, NumElements));
1544 // non-constant ptr can't be folded, keeps it as a v4f32 load
1545 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1546 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
1547 DAG.getConstant(LoadNode->getAddressSpace() -
1548 AMDGPUAS::CONSTANT_BUFFER_0, MVT::i32)
1552 if (!VT.isVector()) {
1553 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1554 DAG.getConstant(0, MVT::i32));
1557 SDValue MergedValues[2] = {
1561 return DAG.getMergeValues(MergedValues, DL);
1564 // For most operations returning SDValue() will result in the node being
1565 // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so we
1566 // need to manually expand loads that may be legal in some address spaces and
1567 // illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported for
1568 // compute shaders, since the data is sign extended when it is uploaded to the
1569 // buffer. However SEXT loads from other address spaces are not supported, so
1570 // we need to expand them here.
1571 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1572 EVT MemVT = LoadNode->getMemoryVT();
1573 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1574 SDValue ShiftAmount =
1575 DAG.getConstant(VT.getSizeInBits() - MemVT.getSizeInBits(), MVT::i32);
1576 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr,
1577 LoadNode->getPointerInfo(), MemVT,
1578 LoadNode->isVolatile(),
1579 LoadNode->isNonTemporal(),
1580 LoadNode->getAlignment());
1581 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, NewLoad, ShiftAmount);
1582 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount);
1584 SDValue MergedValues[2] = { Sra, Chain };
1585 return DAG.getMergeValues(MergedValues, DL);
1588 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1592 // Lowering for indirect addressing
1593 const MachineFunction &MF = DAG.getMachineFunction();
1594 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
1595 getTargetMachine().getFrameLowering());
1596 unsigned StackWidth = TFL->getStackWidth(MF);
1598 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1600 if (VT.isVector()) {
1601 unsigned NumElemVT = VT.getVectorNumElements();
1602 EVT ElemVT = VT.getVectorElementType();
1605 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1606 "vector width in load");
1608 for (unsigned i = 0; i < NumElemVT; ++i) {
1609 unsigned Channel, PtrIncr;
1610 getStackAddress(StackWidth, i, Channel, PtrIncr);
1611 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1612 DAG.getConstant(PtrIncr, MVT::i32));
1613 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
1615 DAG.getTargetConstant(Channel, MVT::i32),
1618 for (unsigned i = NumElemVT; i < 4; ++i) {
1619 Loads[i] = DAG.getUNDEF(ElemVT);
1621 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
1622 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads);
1624 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
1626 DAG.getTargetConstant(0, MVT::i32), // Channel
1635 return DAG.getMergeValues(Ops, DL);
1638 /// XXX Only kernel functions are supported, so we can assume for now that
1639 /// every function is a kernel function, but in the future we should use
1640 /// separate calling conventions for kernel and non-kernel functions.
1641 SDValue R600TargetLowering::LowerFormalArguments(
1643 CallingConv::ID CallConv,
1645 const SmallVectorImpl<ISD::InputArg> &Ins,
1646 SDLoc DL, SelectionDAG &DAG,
1647 SmallVectorImpl<SDValue> &InVals) const {
1648 SmallVector<CCValAssign, 16> ArgLocs;
1649 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1650 getTargetMachine(), ArgLocs, *DAG.getContext());
1651 MachineFunction &MF = DAG.getMachineFunction();
1652 unsigned ShaderType = MF.getInfo<R600MachineFunctionInfo>()->ShaderType;
1654 SmallVector<ISD::InputArg, 8> LocalIns;
1656 getOriginalFunctionArgs(DAG, MF.getFunction(), Ins, LocalIns);
1658 AnalyzeFormalArguments(CCInfo, LocalIns);
1660 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1661 CCValAssign &VA = ArgLocs[i];
1663 EVT MemVT = LocalIns[i].VT;
1665 if (ShaderType != ShaderType::COMPUTE) {
1666 unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass);
1667 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT);
1668 InVals.push_back(Register);
1672 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1673 AMDGPUAS::CONSTANT_BUFFER_0);
1675 // i64 isn't a legal type, so the register type used ends up as i32, which
1676 // isn't expected here. It attempts to create this sextload, but it ends up
1677 // being invalid. Somehow this seems to work with i64 arguments, but breaks
1680 // The first 36 bytes of the input buffer contains information about
1681 // thread group and global sizes.
1683 // FIXME: This should really check the extload type, but the handling of
1684 // extload vecto parameters seems to be broken.
1685 //ISD::LoadExtType Ext = Ins[i].Flags.isSExt() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
1686 ISD::LoadExtType Ext = ISD::SEXTLOAD;
1687 SDValue Arg = DAG.getExtLoad(Ext, DL, VT, Chain,
1688 DAG.getConstant(36 + VA.getLocMemOffset(), MVT::i32),
1689 MachinePointerInfo(UndefValue::get(PtrTy)),
1690 MemVT, false, false, 4);
1692 // 4 is the preferred alignment for the CONSTANT memory space.
1693 InVals.push_back(Arg);
1698 EVT R600TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1701 return VT.changeVectorElementTypeToInteger();
1704 static SDValue CompactSwizzlableVector(
1705 SelectionDAG &DAG, SDValue VectorEntry,
1706 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1707 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1708 assert(RemapSwizzle.empty());
1709 SDValue NewBldVec[4] = {
1710 VectorEntry.getOperand(0),
1711 VectorEntry.getOperand(1),
1712 VectorEntry.getOperand(2),
1713 VectorEntry.getOperand(3)
1716 for (unsigned i = 0; i < 4; i++) {
1717 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1718 // We mask write here to teach later passes that the ith element of this
1719 // vector is undef. Thus we can use it to reduce 128 bits reg usage,
1720 // break false dependencies and additionnaly make assembly easier to read.
1721 RemapSwizzle[i] = 7; // SEL_MASK_WRITE
1722 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) {
1724 RemapSwizzle[i] = 4; // SEL_0
1725 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1726 } else if (C->isExactlyValue(1.0)) {
1727 RemapSwizzle[i] = 5; // SEL_1
1728 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1732 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1734 for (unsigned j = 0; j < i; j++) {
1735 if (NewBldVec[i] == NewBldVec[j]) {
1736 NewBldVec[i] = DAG.getUNDEF(NewBldVec[i].getValueType());
1737 RemapSwizzle[i] = j;
1743 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1744 VectorEntry.getValueType(), NewBldVec);
1747 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1748 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1749 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1750 assert(RemapSwizzle.empty());
1751 SDValue NewBldVec[4] = {
1752 VectorEntry.getOperand(0),
1753 VectorEntry.getOperand(1),
1754 VectorEntry.getOperand(2),
1755 VectorEntry.getOperand(3)
1757 bool isUnmovable[4] = { false, false, false, false };
1758 for (unsigned i = 0; i < 4; i++) {
1759 RemapSwizzle[i] = i;
1760 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1761 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1764 isUnmovable[Idx] = true;
1768 for (unsigned i = 0; i < 4; i++) {
1769 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1770 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1772 if (isUnmovable[Idx])
1775 std::swap(NewBldVec[Idx], NewBldVec[i]);
1776 std::swap(RemapSwizzle[i], RemapSwizzle[Idx]);
1781 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1782 VectorEntry.getValueType(), NewBldVec);
1786 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector,
1787 SDValue Swz[4], SelectionDAG &DAG) const {
1788 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);
1789 // Old -> New swizzle values
1790 DenseMap<unsigned, unsigned> SwizzleRemap;
1792 BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
1793 for (unsigned i = 0; i < 4; i++) {
1794 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1795 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1796 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1799 SwizzleRemap.clear();
1800 BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
1801 for (unsigned i = 0; i < 4; i++) {
1802 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1803 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1804 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1811 //===----------------------------------------------------------------------===//
1812 // Custom DAG Optimizations
1813 //===----------------------------------------------------------------------===//
1815 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1816 DAGCombinerInfo &DCI) const {
1817 SelectionDAG &DAG = DCI.DAG;
1819 switch (N->getOpcode()) {
1820 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1821 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1822 case ISD::FP_ROUND: {
1823 SDValue Arg = N->getOperand(0);
1824 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1825 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0),
1831 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1832 // (i32 select_cc f32, f32, -1, 0 cc)
1834 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1835 // this to one of the SET*_DX10 instructions.
1836 case ISD::FP_TO_SINT: {
1837 SDValue FNeg = N->getOperand(0);
1838 if (FNeg.getOpcode() != ISD::FNEG) {
1841 SDValue SelectCC = FNeg.getOperand(0);
1842 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1843 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1844 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1845 !isHWTrueValue(SelectCC.getOperand(2)) ||
1846 !isHWFalseValue(SelectCC.getOperand(3))) {
1850 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
1851 SelectCC.getOperand(0), // LHS
1852 SelectCC.getOperand(1), // RHS
1853 DAG.getConstant(-1, MVT::i32), // True
1854 DAG.getConstant(0, MVT::i32), // Flase
1855 SelectCC.getOperand(4)); // CC
1860 // insert_vector_elt (build_vector elt0, ... , eltN), NewEltIdx, idx
1861 // => build_vector elt0, ... , NewEltIdx, ... , eltN
1862 case ISD::INSERT_VECTOR_ELT: {
1863 SDValue InVec = N->getOperand(0);
1864 SDValue InVal = N->getOperand(1);
1865 SDValue EltNo = N->getOperand(2);
1868 // If the inserted element is an UNDEF, just use the input vector.
1869 if (InVal.getOpcode() == ISD::UNDEF)
1872 EVT VT = InVec.getValueType();
1874 // If we can't generate a legal BUILD_VECTOR, exit
1875 if (!isOperationLegal(ISD::BUILD_VECTOR, VT))
1878 // Check that we know which element is being inserted
1879 if (!isa<ConstantSDNode>(EltNo))
1881 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
1883 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
1884 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
1886 SmallVector<SDValue, 8> Ops;
1887 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1888 Ops.append(InVec.getNode()->op_begin(),
1889 InVec.getNode()->op_end());
1890 } else if (InVec.getOpcode() == ISD::UNDEF) {
1891 unsigned NElts = VT.getVectorNumElements();
1892 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
1897 // Insert the element
1898 if (Elt < Ops.size()) {
1899 // All the operands of BUILD_VECTOR must have the same type;
1900 // we enforce that here.
1901 EVT OpVT = Ops[0].getValueType();
1902 if (InVal.getValueType() != OpVT)
1903 InVal = OpVT.bitsGT(InVal.getValueType()) ?
1904 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
1905 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
1909 // Return the new vector
1910 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
1913 // Extract_vec (Build_vector) generated by custom lowering
1914 // also needs to be customly combined
1915 case ISD::EXTRACT_VECTOR_ELT: {
1916 SDValue Arg = N->getOperand(0);
1917 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1918 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1919 unsigned Element = Const->getZExtValue();
1920 return Arg->getOperand(Element);
1923 if (Arg.getOpcode() == ISD::BITCAST &&
1924 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1925 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1926 unsigned Element = Const->getZExtValue();
1927 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getVTList(),
1928 Arg->getOperand(0).getOperand(Element));
1933 case ISD::SELECT_CC: {
1934 // Try common optimizations
1935 SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1939 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1940 // selectcc x, y, a, b, inv(cc)
1942 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1943 // selectcc x, y, a, b, cc
1944 SDValue LHS = N->getOperand(0);
1945 if (LHS.getOpcode() != ISD::SELECT_CC) {
1949 SDValue RHS = N->getOperand(1);
1950 SDValue True = N->getOperand(2);
1951 SDValue False = N->getOperand(3);
1952 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1954 if (LHS.getOperand(2).getNode() != True.getNode() ||
1955 LHS.getOperand(3).getNode() != False.getNode() ||
1956 RHS.getNode() != False.getNode()) {
1961 default: return SDValue();
1962 case ISD::SETNE: return LHS;
1964 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1965 LHSCC = ISD::getSetCCInverse(LHSCC,
1966 LHS.getOperand(0).getValueType().isInteger());
1967 if (DCI.isBeforeLegalizeOps() ||
1968 isCondCodeLegal(LHSCC, LHS.getOperand(0).getSimpleValueType()))
1969 return DAG.getSelectCC(SDLoc(N),
1981 case AMDGPUISD::EXPORT: {
1982 SDValue Arg = N->getOperand(1);
1983 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1986 SDValue NewArgs[8] = {
1987 N->getOperand(0), // Chain
1989 N->getOperand(2), // ArrayBase
1990 N->getOperand(3), // Type
1991 N->getOperand(4), // SWZ_X
1992 N->getOperand(5), // SWZ_Y
1993 N->getOperand(6), // SWZ_Z
1994 N->getOperand(7) // SWZ_W
1997 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG);
1998 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs);
2000 case AMDGPUISD::TEXTURE_FETCH: {
2001 SDValue Arg = N->getOperand(1);
2002 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
2005 SDValue NewArgs[19] = {
2026 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG);
2027 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, SDLoc(N), N->getVTList(),
2032 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
2036 FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg,
2037 SDValue &Abs, SDValue &Sel, SDValue &Imm, SelectionDAG &DAG) {
2038 const R600InstrInfo *TII =
2039 static_cast<const R600InstrInfo *>(DAG.getTarget().getInstrInfo());
2040 if (!Src.isMachineOpcode())
2042 switch (Src.getMachineOpcode()) {
2043 case AMDGPU::FNEG_R600:
2046 Src = Src.getOperand(0);
2047 Neg = DAG.getTargetConstant(1, MVT::i32);
2049 case AMDGPU::FABS_R600:
2052 Src = Src.getOperand(0);
2053 Abs = DAG.getTargetConstant(1, MVT::i32);
2055 case AMDGPU::CONST_COPY: {
2056 unsigned Opcode = ParentNode->getMachineOpcode();
2057 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2062 SDValue CstOffset = Src.getOperand(0);
2063 if (ParentNode->getValueType(0).isVector())
2066 // Gather constants values
2067 int SrcIndices[] = {
2068 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
2069 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
2070 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2),
2071 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
2072 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
2073 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
2074 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
2075 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
2076 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
2077 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
2078 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
2080 std::vector<unsigned> Consts;
2081 for (int OtherSrcIdx : SrcIndices) {
2082 int OtherSelIdx = TII->getSelIdx(Opcode, OtherSrcIdx);
2083 if (OtherSrcIdx < 0 || OtherSelIdx < 0)
2089 if (RegisterSDNode *Reg =
2090 dyn_cast<RegisterSDNode>(ParentNode->getOperand(OtherSrcIdx))) {
2091 if (Reg->getReg() == AMDGPU::ALU_CONST) {
2093 = cast<ConstantSDNode>(ParentNode->getOperand(OtherSelIdx));
2094 Consts.push_back(Cst->getZExtValue());
2099 ConstantSDNode *Cst = cast<ConstantSDNode>(CstOffset);
2100 Consts.push_back(Cst->getZExtValue());
2101 if (!TII->fitsConstReadLimitations(Consts)) {
2106 Src = DAG.getRegister(AMDGPU::ALU_CONST, MVT::f32);
2109 case AMDGPU::MOV_IMM_I32:
2110 case AMDGPU::MOV_IMM_F32: {
2111 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
2112 uint64_t ImmValue = 0;
2115 if (Src.getMachineOpcode() == AMDGPU::MOV_IMM_F32) {
2116 ConstantFPSDNode *FPC = dyn_cast<ConstantFPSDNode>(Src.getOperand(0));
2117 float FloatValue = FPC->getValueAPF().convertToFloat();
2118 if (FloatValue == 0.0) {
2119 ImmReg = AMDGPU::ZERO;
2120 } else if (FloatValue == 0.5) {
2121 ImmReg = AMDGPU::HALF;
2122 } else if (FloatValue == 1.0) {
2123 ImmReg = AMDGPU::ONE;
2125 ImmValue = FPC->getValueAPF().bitcastToAPInt().getZExtValue();
2128 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src.getOperand(0));
2129 uint64_t Value = C->getZExtValue();
2131 ImmReg = AMDGPU::ZERO;
2132 } else if (Value == 1) {
2133 ImmReg = AMDGPU::ONE_INT;
2139 // Check that we aren't already using an immediate.
2140 // XXX: It's possible for an instruction to have more than one
2141 // immediate operand, but this is not supported yet.
2142 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
2145 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Imm);
2147 if (C->getZExtValue())
2149 Imm = DAG.getTargetConstant(ImmValue, MVT::i32);
2151 Src = DAG.getRegister(ImmReg, MVT::i32);
2160 /// \brief Fold the instructions after selecting them
2161 SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node,
2162 SelectionDAG &DAG) const {
2163 const R600InstrInfo *TII =
2164 static_cast<const R600InstrInfo *>(DAG.getTarget().getInstrInfo());
2165 if (!Node->isMachineOpcode())
2167 unsigned Opcode = Node->getMachineOpcode();
2170 std::vector<SDValue> Ops;
2171 for(SDNode::op_iterator I = Node->op_begin(), E = Node->op_end();
2175 if (Opcode == AMDGPU::DOT_4) {
2176 int OperandIdx[] = {
2177 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
2178 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
2179 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
2180 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
2181 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
2182 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
2183 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
2184 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
2187 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_X),
2188 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Y),
2189 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Z),
2190 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_W),
2191 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_X),
2192 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Y),
2193 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Z),
2194 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_W)
2197 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_X),
2198 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Y),
2199 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Z),
2200 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_W),
2201 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_X),
2202 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Y),
2203 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Z),
2204 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_W)
2206 for (unsigned i = 0; i < 8; i++) {
2207 if (OperandIdx[i] < 0)
2209 SDValue &Src = Ops[OperandIdx[i] - 1];
2210 SDValue &Neg = Ops[NegIdx[i] - 1];
2211 SDValue &Abs = Ops[AbsIdx[i] - 1];
2212 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2213 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2216 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2217 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, FakeOp, DAG))
2218 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2220 } else if (Opcode == AMDGPU::REG_SEQUENCE) {
2221 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) {
2222 SDValue &Src = Ops[i];
2223 if (FoldOperand(Node, i, Src, FakeOp, FakeOp, FakeOp, FakeOp, DAG))
2224 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2226 } else if (Opcode == AMDGPU::CLAMP_R600) {
2227 SDValue Src = Node->getOperand(0);
2228 if (!Src.isMachineOpcode() ||
2229 !TII->hasInstrModifiers(Src.getMachineOpcode()))
2231 int ClampIdx = TII->getOperandIdx(Src.getMachineOpcode(),
2232 AMDGPU::OpName::clamp);
2235 std::vector<SDValue> Ops;
2236 unsigned NumOp = Src.getNumOperands();
2237 for(unsigned i = 0; i < NumOp; ++i)
2238 Ops.push_back(Src.getOperand(i));
2239 Ops[ClampIdx - 1] = DAG.getTargetConstant(1, MVT::i32);
2240 return DAG.getMachineNode(Src.getMachineOpcode(), SDLoc(Node),
2241 Node->getVTList(), Ops);
2243 if (!TII->hasInstrModifiers(Opcode))
2245 int OperandIdx[] = {
2246 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
2247 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
2248 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2)
2251 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg),
2252 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg),
2253 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2_neg)
2256 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs),
2257 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs),
2260 for (unsigned i = 0; i < 3; i++) {
2261 if (OperandIdx[i] < 0)
2263 SDValue &Src = Ops[OperandIdx[i] - 1];
2264 SDValue &Neg = Ops[NegIdx[i] - 1];
2266 SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
2267 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2268 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2269 int ImmIdx = TII->getOperandIdx(Opcode, AMDGPU::OpName::literal);
2274 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2275 SDValue &Imm = Ops[ImmIdx];
2276 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG))
2277 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);