1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for R600
13 //===----------------------------------------------------------------------===//
15 #include "R600ISelLowering.h"
16 #include "R600Defines.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineFunctionInfo.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Argument.h"
24 #include "llvm/IR/Function.h"
28 R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
29 AMDGPUTargetLowering(TM),
30 TII(static_cast<const R600InstrInfo*>(TM.getInstrInfo())) {
31 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
32 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
33 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
34 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
35 computeRegisterProperties();
37 setOperationAction(ISD::FADD, MVT::v4f32, Expand);
38 setOperationAction(ISD::FMUL, MVT::v4f32, Expand);
39 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
40 setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
42 setOperationAction(ISD::ADD, MVT::v4i32, Expand);
43 setOperationAction(ISD::AND, MVT::v4i32, Expand);
44 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand);
45 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand);
46 setOperationAction(ISD::OR, MVT::v4i32, Expand);
47 setOperationAction(ISD::OR, MVT::v2i32, Expand);
48 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand);
49 setOperationAction(ISD::SHL, MVT::v4i32, Expand);
50 setOperationAction(ISD::SHL, MVT::v2i32, Expand);
51 setOperationAction(ISD::SRL, MVT::v4i32, Expand);
52 setOperationAction(ISD::SRL, MVT::v2i32, Expand);
53 setOperationAction(ISD::SRA, MVT::v4i32, Expand);
54 setOperationAction(ISD::SRA, MVT::v2i32, Expand);
55 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand);
56 setOperationAction(ISD::UDIV, MVT::v4i32, Expand);
57 setOperationAction(ISD::UREM, MVT::v4i32, Expand);
58 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
59 setOperationAction(ISD::XOR, MVT::v4i32, Expand);
60 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
62 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
63 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
65 setOperationAction(ISD::FSUB, MVT::f32, Expand);
67 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
68 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
69 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
71 setOperationAction(ISD::ROTL, MVT::i32, Custom);
73 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
74 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
76 setOperationAction(ISD::SETCC, MVT::i32, Expand);
77 setOperationAction(ISD::SETCC, MVT::f32, Expand);
78 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
80 setOperationAction(ISD::SELECT, MVT::i32, Custom);
81 setOperationAction(ISD::SELECT, MVT::f32, Custom);
83 setOperationAction(ISD::VSELECT, MVT::v4i32, Expand);
84 setOperationAction(ISD::VSELECT, MVT::v2i32, Expand);
86 // Legalize loads and stores to the private address space.
87 setOperationAction(ISD::LOAD, MVT::i32, Custom);
88 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
89 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
90 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
91 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
92 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
93 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Custom);
94 setOperationAction(ISD::STORE, MVT::i8, Custom);
95 setOperationAction(ISD::STORE, MVT::i32, Custom);
96 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
97 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
99 setOperationAction(ISD::LOAD, MVT::i32, Custom);
100 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
101 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
103 setTargetDAGCombine(ISD::FP_ROUND);
104 setTargetDAGCombine(ISD::FP_TO_SINT);
105 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
106 setTargetDAGCombine(ISD::SELECT_CC);
108 setBooleanContents(ZeroOrNegativeOneBooleanContent);
109 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
110 setSchedulingPreference(Sched::VLIW);
113 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
114 MachineInstr * MI, MachineBasicBlock * BB) const {
115 MachineFunction * MF = BB->getParent();
116 MachineRegisterInfo &MRI = MF->getRegInfo();
117 MachineBasicBlock::iterator I = *MI;
119 switch (MI->getOpcode()) {
120 default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
121 case AMDGPU::CLAMP_R600: {
122 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
124 MI->getOperand(0).getReg(),
125 MI->getOperand(1).getReg());
126 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
130 case AMDGPU::FABS_R600: {
131 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
133 MI->getOperand(0).getReg(),
134 MI->getOperand(1).getReg());
135 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
139 case AMDGPU::FNEG_R600: {
140 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
142 MI->getOperand(0).getReg(),
143 MI->getOperand(1).getReg());
144 TII->addFlag(NewMI, 0, MO_FLAG_NEG);
148 case AMDGPU::MASK_WRITE: {
149 unsigned maskedRegister = MI->getOperand(0).getReg();
150 assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
151 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
152 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
156 case AMDGPU::MOV_IMM_F32:
157 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
158 MI->getOperand(1).getFPImm()->getValueAPF()
159 .bitcastToAPInt().getZExtValue());
161 case AMDGPU::MOV_IMM_I32:
162 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
163 MI->getOperand(1).getImm());
165 case AMDGPU::CONST_COPY: {
166 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
167 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
168 TII->setImmOperand(NewMI, R600Operands::SRC0_SEL,
169 MI->getOperand(1).getImm());
173 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
174 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
175 unsigned EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
177 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
178 .addOperand(MI->getOperand(0))
179 .addOperand(MI->getOperand(1))
180 .addImm(EOP); // Set End of program bit
185 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
186 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
188 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
189 .addOperand(MI->getOperand(3))
190 .addOperand(MI->getOperand(4))
191 .addOperand(MI->getOperand(5))
192 .addOperand(MI->getOperand(6));
193 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
194 .addOperand(MI->getOperand(2))
195 .addOperand(MI->getOperand(4))
196 .addOperand(MI->getOperand(5))
197 .addOperand(MI->getOperand(6));
198 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
199 .addOperand(MI->getOperand(0))
200 .addOperand(MI->getOperand(1))
201 .addOperand(MI->getOperand(4))
202 .addOperand(MI->getOperand(5))
203 .addOperand(MI->getOperand(6))
204 .addReg(T0, RegState::Implicit)
205 .addReg(T1, RegState::Implicit);
209 case AMDGPU::TXD_SHADOW: {
210 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
211 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
213 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
214 .addOperand(MI->getOperand(3))
215 .addOperand(MI->getOperand(4))
216 .addOperand(MI->getOperand(5))
217 .addOperand(MI->getOperand(6));
218 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
219 .addOperand(MI->getOperand(2))
220 .addOperand(MI->getOperand(4))
221 .addOperand(MI->getOperand(5))
222 .addOperand(MI->getOperand(6));
223 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
224 .addOperand(MI->getOperand(0))
225 .addOperand(MI->getOperand(1))
226 .addOperand(MI->getOperand(4))
227 .addOperand(MI->getOperand(5))
228 .addOperand(MI->getOperand(6))
229 .addReg(T0, RegState::Implicit)
230 .addReg(T1, RegState::Implicit);
235 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
236 .addOperand(MI->getOperand(0));
239 case AMDGPU::BRANCH_COND_f32: {
240 MachineInstr *NewMI =
241 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
242 AMDGPU::PREDICATE_BIT)
243 .addOperand(MI->getOperand(1))
244 .addImm(OPCODE_IS_NOT_ZERO)
246 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
247 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
248 .addOperand(MI->getOperand(0))
249 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
253 case AMDGPU::BRANCH_COND_i32: {
254 MachineInstr *NewMI =
255 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
256 AMDGPU::PREDICATE_BIT)
257 .addOperand(MI->getOperand(1))
258 .addImm(OPCODE_IS_NOT_ZERO_INT)
260 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
261 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
262 .addOperand(MI->getOperand(0))
263 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
267 case AMDGPU::EG_ExportSwz:
268 case AMDGPU::R600_ExportSwz: {
269 // Instruction is left unmodified if its not the last one of its type
270 bool isLastInstructionOfItsType = true;
271 unsigned InstExportType = MI->getOperand(1).getImm();
272 for (MachineBasicBlock::iterator NextExportInst = llvm::next(I),
273 EndBlock = BB->end(); NextExportInst != EndBlock;
274 NextExportInst = llvm::next(NextExportInst)) {
275 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
276 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
277 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
279 if (CurrentInstExportType == InstExportType) {
280 isLastInstructionOfItsType = false;
285 bool EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN)? 1 : 0;
286 if (!EOP && !isLastInstructionOfItsType)
288 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
289 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
290 .addOperand(MI->getOperand(0))
291 .addOperand(MI->getOperand(1))
292 .addOperand(MI->getOperand(2))
293 .addOperand(MI->getOperand(3))
294 .addOperand(MI->getOperand(4))
295 .addOperand(MI->getOperand(5))
296 .addOperand(MI->getOperand(6))
301 case AMDGPU::RETURN: {
302 // RETURN instructions must have the live-out registers as implicit uses,
303 // otherwise they appear dead.
304 R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
305 MachineInstrBuilder MIB(*MF, MI);
306 for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
307 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
312 MI->eraseFromParent();
316 //===----------------------------------------------------------------------===//
317 // Custom DAG Lowering Operations
318 //===----------------------------------------------------------------------===//
320 using namespace llvm::Intrinsic;
321 using namespace llvm::AMDGPUIntrinsic;
323 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
324 switch (Op.getOpcode()) {
325 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
326 case ISD::ROTL: return LowerROTL(Op, DAG);
327 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
328 case ISD::SELECT: return LowerSELECT(Op, DAG);
329 case ISD::STORE: return LowerSTORE(Op, DAG);
330 case ISD::LOAD: return LowerLOAD(Op, DAG);
331 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
332 case ISD::INTRINSIC_VOID: {
333 SDValue Chain = Op.getOperand(0);
334 unsigned IntrinsicID =
335 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
336 switch (IntrinsicID) {
337 case AMDGPUIntrinsic::AMDGPU_store_output: {
338 MachineFunction &MF = DAG.getMachineFunction();
339 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
340 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
341 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
342 MFI->LiveOuts.push_back(Reg);
343 return DAG.getCopyToReg(Chain, Op.getDebugLoc(), Reg, Op.getOperand(2));
345 case AMDGPUIntrinsic::R600_store_swizzle: {
346 const SDValue Args[8] = {
348 Op.getOperand(2), // Export Value
349 Op.getOperand(3), // ArrayBase
350 Op.getOperand(4), // Type
351 DAG.getConstant(0, MVT::i32), // SWZ_X
352 DAG.getConstant(1, MVT::i32), // SWZ_Y
353 DAG.getConstant(2, MVT::i32), // SWZ_Z
354 DAG.getConstant(3, MVT::i32) // SWZ_W
356 return DAG.getNode(AMDGPUISD::EXPORT, Op.getDebugLoc(), Op.getValueType(),
360 // default for switch(IntrinsicID)
363 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
366 case ISD::INTRINSIC_WO_CHAIN: {
367 unsigned IntrinsicID =
368 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
369 EVT VT = Op.getValueType();
370 DebugLoc DL = Op.getDebugLoc();
371 switch(IntrinsicID) {
372 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
373 case AMDGPUIntrinsic::R600_load_input: {
374 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
375 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
376 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
379 case AMDGPUIntrinsic::R600_interp_input: {
380 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
381 int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
382 MachineSDNode *interp;
384 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
385 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
386 return DAG.getTargetExtractSubreg(
387 TII->getRegisterInfo().getSubRegFromChannel(slot % 4),
388 DL, MVT::f32, SDValue(interp, 0));
392 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
393 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
394 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
395 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1), MVT::f32),
396 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
397 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb), MVT::f32));
399 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
400 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
401 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
402 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1), MVT::f32),
403 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
404 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb), MVT::f32));
406 return SDValue(interp, slot % 2);
409 case r600_read_ngroups_x:
410 return LowerImplicitParameter(DAG, VT, DL, 0);
411 case r600_read_ngroups_y:
412 return LowerImplicitParameter(DAG, VT, DL, 1);
413 case r600_read_ngroups_z:
414 return LowerImplicitParameter(DAG, VT, DL, 2);
415 case r600_read_global_size_x:
416 return LowerImplicitParameter(DAG, VT, DL, 3);
417 case r600_read_global_size_y:
418 return LowerImplicitParameter(DAG, VT, DL, 4);
419 case r600_read_global_size_z:
420 return LowerImplicitParameter(DAG, VT, DL, 5);
421 case r600_read_local_size_x:
422 return LowerImplicitParameter(DAG, VT, DL, 6);
423 case r600_read_local_size_y:
424 return LowerImplicitParameter(DAG, VT, DL, 7);
425 case r600_read_local_size_z:
426 return LowerImplicitParameter(DAG, VT, DL, 8);
428 case r600_read_tgid_x:
429 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
431 case r600_read_tgid_y:
432 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
434 case r600_read_tgid_z:
435 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
437 case r600_read_tidig_x:
438 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
440 case r600_read_tidig_y:
441 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
443 case r600_read_tidig_z:
444 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
447 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
450 } // end switch(Op.getOpcode())
454 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
455 SmallVectorImpl<SDValue> &Results,
456 SelectionDAG &DAG) const {
457 switch (N->getOpcode()) {
459 case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
462 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
463 Results.push_back(SDValue(Node, 0));
464 Results.push_back(SDValue(Node, 1));
465 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
467 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
471 SDNode *Node = LowerSTORE(SDValue(N, 0), DAG).getNode();
472 Results.push_back(SDValue(Node, 0));
477 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
482 Op, DAG.getConstantFP(0.0f, MVT::f32),
483 DAG.getCondCode(ISD::SETNE)
487 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
489 unsigned DwordOffset) const {
490 unsigned ByteOffset = DwordOffset * 4;
491 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
492 AMDGPUAS::PARAM_I_ADDRESS);
494 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
495 assert(isInt<16>(ByteOffset));
497 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
498 DAG.getConstant(ByteOffset, MVT::i32), // PTR
499 MachinePointerInfo(ConstantPointerNull::get(PtrType)),
500 false, false, false, 0);
503 SDValue R600TargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
505 MachineFunction &MF = DAG.getMachineFunction();
506 const AMDGPUFrameLowering *TFL =
507 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
509 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op);
512 unsigned FrameIndex = FIN->getIndex();
513 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
514 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), MVT::i32);
517 SDValue R600TargetLowering::LowerROTL(SDValue Op, SelectionDAG &DAG) const {
518 DebugLoc DL = Op.getDebugLoc();
519 EVT VT = Op.getValueType();
521 return DAG.getNode(AMDGPUISD::BITALIGN, DL, VT,
524 DAG.getNode(ISD::SUB, DL, VT,
525 DAG.getConstant(32, MVT::i32),
529 bool R600TargetLowering::isZero(SDValue Op) const {
530 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
531 return Cst->isNullValue();
532 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
533 return CstFP->isZero();
539 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
540 DebugLoc DL = Op.getDebugLoc();
541 EVT VT = Op.getValueType();
543 SDValue LHS = Op.getOperand(0);
544 SDValue RHS = Op.getOperand(1);
545 SDValue True = Op.getOperand(2);
546 SDValue False = Op.getOperand(3);
547 SDValue CC = Op.getOperand(4);
550 // LHS and RHS are guaranteed to be the same value type
551 EVT CompareVT = LHS.getValueType();
553 // Check if we can lower this to a native operation.
555 // Try to lower to a SET* instruction:
557 // SET* can match the following patterns:
559 // select_cc f32, f32, -1, 0, cc_any
560 // select_cc f32, f32, 1.0f, 0.0f, cc_any
561 // select_cc i32, i32, -1, 0, cc_any
564 // Move hardware True/False values to the correct operand.
565 if (isHWTrueValue(False) && isHWFalseValue(True)) {
566 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
567 std::swap(False, True);
568 CC = DAG.getCondCode(ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32));
571 if (isHWTrueValue(True) && isHWFalseValue(False) &&
572 (CompareVT == VT || VT == MVT::i32)) {
573 // This can be matched by a SET* instruction.
574 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
577 // Try to lower to a CND* instruction:
579 // CND* can match the following patterns:
581 // select_cc f32, 0.0, f32, f32, cc_any
582 // select_cc f32, 0.0, i32, i32, cc_any
583 // select_cc i32, 0, f32, f32, cc_any
584 // select_cc i32, 0, i32, i32, cc_any
586 if (isZero(LHS) || isZero(RHS)) {
587 SDValue Cond = (isZero(LHS) ? RHS : LHS);
588 SDValue Zero = (isZero(LHS) ? LHS : RHS);
589 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
590 if (CompareVT != VT) {
591 // Bitcast True / False to the correct types. This will end up being
592 // a nop, but it allows us to define only a single pattern in the
593 // .TD files for each CND* instruction rather than having to have
594 // one pattern for integer True/False and one for fp True/False
595 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
596 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
599 CCOpcode = ISD::getSetCCSwappedOperands(CCOpcode);
612 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
620 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
623 DAG.getCondCode(CCOpcode));
624 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
628 // Possible Min/Max pattern
629 SDValue MinMax = LowerMinMax(Op, DAG);
630 if (MinMax.getNode()) {
634 // If we make it this for it means we have no native instructions to handle
635 // this SELECT_CC, so we must lower it.
636 SDValue HWTrue, HWFalse;
638 if (CompareVT == MVT::f32) {
639 HWTrue = DAG.getConstantFP(1.0f, CompareVT);
640 HWFalse = DAG.getConstantFP(0.0f, CompareVT);
641 } else if (CompareVT == MVT::i32) {
642 HWTrue = DAG.getConstant(-1, CompareVT);
643 HWFalse = DAG.getConstant(0, CompareVT);
646 assert(!"Unhandled value type in LowerSELECT_CC");
649 // Lower this unsupported SELECT_CC into a combination of two supported
650 // SELECT_CC operations.
651 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
653 return DAG.getNode(ISD::SELECT_CC, DL, VT,
656 DAG.getCondCode(ISD::SETNE));
659 SDValue R600TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
660 return DAG.getNode(ISD::SELECT_CC,
664 DAG.getConstant(0, MVT::i32),
667 DAG.getCondCode(ISD::SETNE));
670 /// LLVM generates byte-addresed pointers. For indirect addressing, we need to
671 /// convert these pointers to a register index. Each register holds
672 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
673 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
674 /// for indirect addressing.
675 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
677 SelectionDAG &DAG) const {
689 default: llvm_unreachable("Invalid stack width");
692 return DAG.getNode(ISD::SRL, Ptr.getDebugLoc(), Ptr.getValueType(), Ptr,
693 DAG.getConstant(SRLPad, MVT::i32));
696 void R600TargetLowering::getStackAddress(unsigned StackWidth,
699 unsigned &PtrIncr) const {
700 switch (StackWidth) {
711 Channel = ElemIdx % 2;
725 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
726 DebugLoc DL = Op.getDebugLoc();
727 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
728 SDValue Chain = Op.getOperand(0);
729 SDValue Value = Op.getOperand(1);
730 SDValue Ptr = Op.getOperand(2);
732 if (StoreNode->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
733 Ptr->getOpcode() != AMDGPUISD::DWORDADDR) {
734 // Convert pointer from byte address to dword address.
735 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
736 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
737 Ptr, DAG.getConstant(2, MVT::i32)));
739 if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
740 assert(!"Truncated and indexed stores not supported yet");
742 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
747 EVT ValueVT = Value.getValueType();
749 if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
753 // Lowering for indirect addressing
755 const MachineFunction &MF = DAG.getMachineFunction();
756 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
757 getTargetMachine().getFrameLowering());
758 unsigned StackWidth = TFL->getStackWidth(MF);
760 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
762 if (ValueVT.isVector()) {
763 unsigned NumElemVT = ValueVT.getVectorNumElements();
764 EVT ElemVT = ValueVT.getVectorElementType();
767 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
768 "vector width in load");
770 for (unsigned i = 0; i < NumElemVT; ++i) {
771 unsigned Channel, PtrIncr;
772 getStackAddress(StackWidth, i, Channel, PtrIncr);
773 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
774 DAG.getConstant(PtrIncr, MVT::i32));
775 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
776 Value, DAG.getConstant(i, MVT::i32));
778 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
780 DAG.getTargetConstant(Channel, MVT::i32));
782 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores, NumElemVT);
784 if (ValueVT == MVT::i8) {
785 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
787 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
788 DAG.getTargetConstant(0, MVT::i32)); // Channel
794 // return (512 + (kc_bank << 12)
796 ConstantAddressBlock(unsigned AddressSpace) {
797 switch (AddressSpace) {
798 case AMDGPUAS::CONSTANT_BUFFER_0:
800 case AMDGPUAS::CONSTANT_BUFFER_1:
802 case AMDGPUAS::CONSTANT_BUFFER_2:
803 return 512 + 4096 * 2;
804 case AMDGPUAS::CONSTANT_BUFFER_3:
805 return 512 + 4096 * 3;
806 case AMDGPUAS::CONSTANT_BUFFER_4:
807 return 512 + 4096 * 4;
808 case AMDGPUAS::CONSTANT_BUFFER_5:
809 return 512 + 4096 * 5;
810 case AMDGPUAS::CONSTANT_BUFFER_6:
811 return 512 + 4096 * 6;
812 case AMDGPUAS::CONSTANT_BUFFER_7:
813 return 512 + 4096 * 7;
814 case AMDGPUAS::CONSTANT_BUFFER_8:
815 return 512 + 4096 * 8;
816 case AMDGPUAS::CONSTANT_BUFFER_9:
817 return 512 + 4096 * 9;
818 case AMDGPUAS::CONSTANT_BUFFER_10:
819 return 512 + 4096 * 10;
820 case AMDGPUAS::CONSTANT_BUFFER_11:
821 return 512 + 4096 * 11;
822 case AMDGPUAS::CONSTANT_BUFFER_12:
823 return 512 + 4096 * 12;
824 case AMDGPUAS::CONSTANT_BUFFER_13:
825 return 512 + 4096 * 13;
826 case AMDGPUAS::CONSTANT_BUFFER_14:
827 return 512 + 4096 * 14;
828 case AMDGPUAS::CONSTANT_BUFFER_15:
829 return 512 + 4096 * 15;
835 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
837 EVT VT = Op.getValueType();
838 DebugLoc DL = Op.getDebugLoc();
839 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
840 SDValue Chain = Op.getOperand(0);
841 SDValue Ptr = Op.getOperand(1);
844 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
845 if (ConstantBlock > -1) {
847 if (dyn_cast<ConstantExpr>(LoadNode->getSrcValue()) ||
848 dyn_cast<Constant>(LoadNode->getSrcValue()) ||
849 dyn_cast<ConstantSDNode>(Ptr)) {
851 for (unsigned i = 0; i < 4; i++) {
852 // We want Const position encoded with the following formula :
853 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
854 // const_index is Ptr computed by llvm using an alignment of 16.
855 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
856 // then div by 4 at the ISel step
857 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
858 DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
859 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
861 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Slots, 4);
863 // non constant ptr cant be folded, keeps it as a v4f32 load
864 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
865 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
866 DAG.getConstant(LoadNode->getAddressSpace() -
867 AMDGPUAS::CONSTANT_BUFFER_0, MVT::i32)
871 if (!VT.isVector()) {
872 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
873 DAG.getConstant(0, MVT::i32));
876 SDValue MergedValues[2] = {
880 return DAG.getMergeValues(MergedValues, 2, DL);
883 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
887 // Lowering for indirect addressing
888 const MachineFunction &MF = DAG.getMachineFunction();
889 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
890 getTargetMachine().getFrameLowering());
891 unsigned StackWidth = TFL->getStackWidth(MF);
893 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
896 unsigned NumElemVT = VT.getVectorNumElements();
897 EVT ElemVT = VT.getVectorElementType();
900 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
901 "vector width in load");
903 for (unsigned i = 0; i < NumElemVT; ++i) {
904 unsigned Channel, PtrIncr;
905 getStackAddress(StackWidth, i, Channel, PtrIncr);
906 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
907 DAG.getConstant(PtrIncr, MVT::i32));
908 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
910 DAG.getTargetConstant(Channel, MVT::i32),
913 for (unsigned i = NumElemVT; i < 4; ++i) {
914 Loads[i] = DAG.getUNDEF(ElemVT);
916 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
917 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads, 4);
919 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
921 DAG.getTargetConstant(0, MVT::i32), // Channel
926 Ops[0] = LoweredLoad;
929 return DAG.getMergeValues(Ops, 2, DL);
932 /// XXX Only kernel functions are supported, so we can assume for now that
933 /// every function is a kernel function, but in the future we should use
934 /// separate calling conventions for kernel and non-kernel functions.
935 SDValue R600TargetLowering::LowerFormalArguments(
937 CallingConv::ID CallConv,
939 const SmallVectorImpl<ISD::InputArg> &Ins,
940 DebugLoc DL, SelectionDAG &DAG,
941 SmallVectorImpl<SDValue> &InVals) const {
942 unsigned ParamOffsetBytes = 36;
943 Function::const_arg_iterator FuncArg =
944 DAG.getMachineFunction().getFunction()->arg_begin();
945 for (unsigned i = 0, e = Ins.size(); i < e; ++i, ++FuncArg) {
947 Type *ArgType = FuncArg->getType();
948 unsigned ArgSizeInBits = ArgType->isPointerTy() ?
949 32 : ArgType->getPrimitiveSizeInBits();
950 unsigned ArgBytes = ArgSizeInBits >> 3;
952 if (ArgSizeInBits < VT.getSizeInBits()) {
953 assert(!ArgType->isFloatTy() &&
954 "Extending floating point arguments not supported yet");
955 ArgVT = MVT::getIntegerVT(ArgSizeInBits);
959 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
960 AMDGPUAS::PARAM_I_ADDRESS);
961 SDValue Arg = DAG.getExtLoad(ISD::ZEXTLOAD, DL, VT, DAG.getRoot(),
962 DAG.getConstant(ParamOffsetBytes, MVT::i32),
963 MachinePointerInfo(UndefValue::get(PtrTy)),
964 ArgVT, false, false, ArgBytes);
965 InVals.push_back(Arg);
966 ParamOffsetBytes += ArgBytes;
971 EVT R600TargetLowering::getSetCCResultType(EVT VT) const {
972 if (!VT.isVector()) return MVT::i32;
973 return VT.changeVectorElementTypeToInteger();
976 //===----------------------------------------------------------------------===//
977 // Custom DAG Optimizations
978 //===----------------------------------------------------------------------===//
980 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
981 DAGCombinerInfo &DCI) const {
982 SelectionDAG &DAG = DCI.DAG;
984 switch (N->getOpcode()) {
985 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
986 case ISD::FP_ROUND: {
987 SDValue Arg = N->getOperand(0);
988 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
989 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), N->getValueType(0),
995 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
996 // (i32 select_cc f32, f32, -1, 0 cc)
998 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
999 // this to one of the SET*_DX10 instructions.
1000 case ISD::FP_TO_SINT: {
1001 SDValue FNeg = N->getOperand(0);
1002 if (FNeg.getOpcode() != ISD::FNEG) {
1005 SDValue SelectCC = FNeg.getOperand(0);
1006 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1007 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1008 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1009 !isHWTrueValue(SelectCC.getOperand(2)) ||
1010 !isHWFalseValue(SelectCC.getOperand(3))) {
1014 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N->getValueType(0),
1015 SelectCC.getOperand(0), // LHS
1016 SelectCC.getOperand(1), // RHS
1017 DAG.getConstant(-1, MVT::i32), // True
1018 DAG.getConstant(0, MVT::i32), // Flase
1019 SelectCC.getOperand(4)); // CC
1023 // Extract_vec (Build_vector) generated by custom lowering
1024 // also needs to be customly combined
1025 case ISD::EXTRACT_VECTOR_ELT: {
1026 SDValue Arg = N->getOperand(0);
1027 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1028 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1029 unsigned Element = Const->getZExtValue();
1030 return Arg->getOperand(Element);
1033 if (Arg.getOpcode() == ISD::BITCAST &&
1034 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1035 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1036 unsigned Element = Const->getZExtValue();
1037 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getVTList(),
1038 Arg->getOperand(0).getOperand(Element));
1043 case ISD::SELECT_CC: {
1044 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1045 // selectcc x, y, a, b, inv(cc)
1047 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1048 // selectcc x, y, a, b, cc
1049 SDValue LHS = N->getOperand(0);
1050 if (LHS.getOpcode() != ISD::SELECT_CC) {
1054 SDValue RHS = N->getOperand(1);
1055 SDValue True = N->getOperand(2);
1056 SDValue False = N->getOperand(3);
1057 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1059 if (LHS.getOperand(2).getNode() != True.getNode() ||
1060 LHS.getOperand(3).getNode() != False.getNode() ||
1061 RHS.getNode() != False.getNode()) {
1066 default: return SDValue();
1067 case ISD::SETNE: return LHS;
1069 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1070 LHSCC = ISD::getSetCCInverse(LHSCC,
1071 LHS.getOperand(0).getValueType().isInteger());
1072 return DAG.getSelectCC(N->getDebugLoc(),
1081 case AMDGPUISD::EXPORT: {
1082 SDValue Arg = N->getOperand(1);
1083 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1085 SDValue NewBldVec[4] = {
1086 DAG.getUNDEF(MVT::f32),
1087 DAG.getUNDEF(MVT::f32),
1088 DAG.getUNDEF(MVT::f32),
1089 DAG.getUNDEF(MVT::f32)
1091 SDValue NewArgs[8] = {
1092 N->getOperand(0), // Chain
1094 N->getOperand(2), // ArrayBase
1095 N->getOperand(3), // Type
1096 N->getOperand(4), // SWZ_X
1097 N->getOperand(5), // SWZ_Y
1098 N->getOperand(6), // SWZ_Z
1099 N->getOperand(7) // SWZ_W
1101 for (unsigned i = 0; i < Arg.getNumOperands(); i++) {
1102 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Arg.getOperand(i))) {
1104 NewArgs[4 + i] = DAG.getConstant(4, MVT::i32); // SEL_0
1105 } else if (C->isExactlyValue(1.0)) {
1106 NewArgs[4 + i] = DAG.getConstant(5, MVT::i32); // SEL_0
1108 NewBldVec[i] = Arg.getOperand(i);
1111 NewBldVec[i] = Arg.getOperand(i);
1114 DebugLoc DL = N->getDebugLoc();
1115 NewArgs[1] = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4f32, NewBldVec, 4);
1116 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs, 8);