1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for R600
13 //===----------------------------------------------------------------------===//
15 #include "R600ISelLowering.h"
16 #include "R600Defines.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineFunctionInfo.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Argument.h"
24 #include "llvm/IR/Function.h"
28 R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
29 AMDGPUTargetLowering(TM),
30 TII(static_cast<const R600InstrInfo*>(TM.getInstrInfo())) {
31 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
32 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
33 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
34 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
35 computeRegisterProperties();
37 setOperationAction(ISD::FADD, MVT::v4f32, Expand);
38 setOperationAction(ISD::FMUL, MVT::v4f32, Expand);
39 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
40 setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
42 setOperationAction(ISD::ADD, MVT::v4i32, Expand);
43 setOperationAction(ISD::AND, MVT::v4i32, Expand);
44 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand);
45 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand);
46 setOperationAction(ISD::MUL, MVT::v2i32, Expand);
47 setOperationAction(ISD::MUL, MVT::v4i32, Expand);
48 setOperationAction(ISD::OR, MVT::v4i32, Expand);
49 setOperationAction(ISD::OR, MVT::v2i32, Expand);
50 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand);
51 setOperationAction(ISD::SHL, MVT::v4i32, Expand);
52 setOperationAction(ISD::SHL, MVT::v2i32, Expand);
53 setOperationAction(ISD::SRL, MVT::v4i32, Expand);
54 setOperationAction(ISD::SRL, MVT::v2i32, Expand);
55 setOperationAction(ISD::SRA, MVT::v4i32, Expand);
56 setOperationAction(ISD::SRA, MVT::v2i32, Expand);
57 setOperationAction(ISD::SUB, MVT::v4i32, Expand);
58 setOperationAction(ISD::SUB, MVT::v2i32, Expand);
59 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand);
60 setOperationAction(ISD::UDIV, MVT::v4i32, Expand);
61 setOperationAction(ISD::UREM, MVT::v4i32, Expand);
62 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
63 setOperationAction(ISD::XOR, MVT::v4i32, Expand);
64 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
66 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
67 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
69 setOperationAction(ISD::FSUB, MVT::f32, Expand);
71 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
72 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
73 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
75 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
76 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
78 setOperationAction(ISD::SETCC, MVT::i32, Expand);
79 setOperationAction(ISD::SETCC, MVT::f32, Expand);
80 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
82 setOperationAction(ISD::SELECT, MVT::i32, Custom);
83 setOperationAction(ISD::SELECT, MVT::f32, Custom);
85 setOperationAction(ISD::VSELECT, MVT::v4i32, Expand);
86 setOperationAction(ISD::VSELECT, MVT::v2i32, Expand);
88 // Legalize loads and stores to the private address space.
89 setOperationAction(ISD::LOAD, MVT::i32, Custom);
90 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
91 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
92 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
93 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
94 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
95 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Custom);
96 setOperationAction(ISD::STORE, MVT::i8, Custom);
97 setOperationAction(ISD::STORE, MVT::i32, Custom);
98 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
99 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
101 setOperationAction(ISD::LOAD, MVT::i32, Custom);
102 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
103 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
105 setTargetDAGCombine(ISD::FP_ROUND);
106 setTargetDAGCombine(ISD::FP_TO_SINT);
107 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
108 setTargetDAGCombine(ISD::SELECT_CC);
110 setBooleanContents(ZeroOrNegativeOneBooleanContent);
111 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
112 setSchedulingPreference(Sched::VLIW);
115 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
116 MachineInstr * MI, MachineBasicBlock * BB) const {
117 MachineFunction * MF = BB->getParent();
118 MachineRegisterInfo &MRI = MF->getRegInfo();
119 MachineBasicBlock::iterator I = *MI;
121 switch (MI->getOpcode()) {
122 default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
123 case AMDGPU::CLAMP_R600: {
124 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
126 MI->getOperand(0).getReg(),
127 MI->getOperand(1).getReg());
128 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
132 case AMDGPU::FABS_R600: {
133 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
135 MI->getOperand(0).getReg(),
136 MI->getOperand(1).getReg());
137 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
141 case AMDGPU::FNEG_R600: {
142 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
144 MI->getOperand(0).getReg(),
145 MI->getOperand(1).getReg());
146 TII->addFlag(NewMI, 0, MO_FLAG_NEG);
150 case AMDGPU::MASK_WRITE: {
151 unsigned maskedRegister = MI->getOperand(0).getReg();
152 assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
153 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
154 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
158 case AMDGPU::MOV_IMM_F32:
159 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
160 MI->getOperand(1).getFPImm()->getValueAPF()
161 .bitcastToAPInt().getZExtValue());
163 case AMDGPU::MOV_IMM_I32:
164 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
165 MI->getOperand(1).getImm());
167 case AMDGPU::CONST_COPY: {
168 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
169 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
170 TII->setImmOperand(NewMI, R600Operands::SRC0_SEL,
171 MI->getOperand(1).getImm());
175 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
176 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
177 unsigned EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
179 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
180 .addOperand(MI->getOperand(0))
181 .addOperand(MI->getOperand(1))
182 .addImm(EOP); // Set End of program bit
187 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
188 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
189 MachineOperand &RID = MI->getOperand(4);
190 MachineOperand &SID = MI->getOperand(5);
191 unsigned TextureId = MI->getOperand(6).getImm();
192 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
193 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
205 case 8: // ShadowRect
216 case 11: // Shadow1DArray
220 case 12: // Shadow2DArray
224 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
225 .addOperand(MI->getOperand(3))
243 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
244 .addOperand(MI->getOperand(2))
262 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
263 .addOperand(MI->getOperand(0))
264 .addOperand(MI->getOperand(1))
282 .addReg(T0, RegState::Implicit)
283 .addReg(T1, RegState::Implicit);
287 case AMDGPU::TXD_SHADOW: {
288 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
289 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
290 MachineOperand &RID = MI->getOperand(4);
291 MachineOperand &SID = MI->getOperand(5);
292 unsigned TextureId = MI->getOperand(6).getImm();
293 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
294 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
306 case 8: // ShadowRect
317 case 11: // Shadow1DArray
321 case 12: // Shadow2DArray
326 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
327 .addOperand(MI->getOperand(3))
345 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
346 .addOperand(MI->getOperand(2))
364 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
365 .addOperand(MI->getOperand(0))
366 .addOperand(MI->getOperand(1))
384 .addReg(T0, RegState::Implicit)
385 .addReg(T1, RegState::Implicit);
390 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
391 .addOperand(MI->getOperand(0));
394 case AMDGPU::BRANCH_COND_f32: {
395 MachineInstr *NewMI =
396 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
397 AMDGPU::PREDICATE_BIT)
398 .addOperand(MI->getOperand(1))
399 .addImm(OPCODE_IS_NOT_ZERO)
401 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
402 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
403 .addOperand(MI->getOperand(0))
404 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
408 case AMDGPU::BRANCH_COND_i32: {
409 MachineInstr *NewMI =
410 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
411 AMDGPU::PREDICATE_BIT)
412 .addOperand(MI->getOperand(1))
413 .addImm(OPCODE_IS_NOT_ZERO_INT)
415 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
416 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
417 .addOperand(MI->getOperand(0))
418 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
422 case AMDGPU::EG_ExportSwz:
423 case AMDGPU::R600_ExportSwz: {
424 // Instruction is left unmodified if its not the last one of its type
425 bool isLastInstructionOfItsType = true;
426 unsigned InstExportType = MI->getOperand(1).getImm();
427 for (MachineBasicBlock::iterator NextExportInst = llvm::next(I),
428 EndBlock = BB->end(); NextExportInst != EndBlock;
429 NextExportInst = llvm::next(NextExportInst)) {
430 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
431 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
432 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
434 if (CurrentInstExportType == InstExportType) {
435 isLastInstructionOfItsType = false;
440 bool EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN)? 1 : 0;
441 if (!EOP && !isLastInstructionOfItsType)
443 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
444 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
445 .addOperand(MI->getOperand(0))
446 .addOperand(MI->getOperand(1))
447 .addOperand(MI->getOperand(2))
448 .addOperand(MI->getOperand(3))
449 .addOperand(MI->getOperand(4))
450 .addOperand(MI->getOperand(5))
451 .addOperand(MI->getOperand(6))
456 case AMDGPU::RETURN: {
457 // RETURN instructions must have the live-out registers as implicit uses,
458 // otherwise they appear dead.
459 R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
460 MachineInstrBuilder MIB(*MF, MI);
461 for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
462 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
467 MI->eraseFromParent();
471 //===----------------------------------------------------------------------===//
472 // Custom DAG Lowering Operations
473 //===----------------------------------------------------------------------===//
475 using namespace llvm::Intrinsic;
476 using namespace llvm::AMDGPUIntrinsic;
478 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
479 switch (Op.getOpcode()) {
480 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
481 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
482 case ISD::SELECT: return LowerSELECT(Op, DAG);
483 case ISD::STORE: return LowerSTORE(Op, DAG);
484 case ISD::LOAD: return LowerLOAD(Op, DAG);
485 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
486 case ISD::INTRINSIC_VOID: {
487 SDValue Chain = Op.getOperand(0);
488 unsigned IntrinsicID =
489 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
490 switch (IntrinsicID) {
491 case AMDGPUIntrinsic::AMDGPU_store_output: {
492 MachineFunction &MF = DAG.getMachineFunction();
493 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
494 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
495 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
496 MFI->LiveOuts.push_back(Reg);
497 return DAG.getCopyToReg(Chain, Op.getDebugLoc(), Reg, Op.getOperand(2));
499 case AMDGPUIntrinsic::R600_store_swizzle: {
500 const SDValue Args[8] = {
502 Op.getOperand(2), // Export Value
503 Op.getOperand(3), // ArrayBase
504 Op.getOperand(4), // Type
505 DAG.getConstant(0, MVT::i32), // SWZ_X
506 DAG.getConstant(1, MVT::i32), // SWZ_Y
507 DAG.getConstant(2, MVT::i32), // SWZ_Z
508 DAG.getConstant(3, MVT::i32) // SWZ_W
510 return DAG.getNode(AMDGPUISD::EXPORT, Op.getDebugLoc(), Op.getValueType(),
514 // default for switch(IntrinsicID)
517 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
520 case ISD::INTRINSIC_WO_CHAIN: {
521 unsigned IntrinsicID =
522 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
523 EVT VT = Op.getValueType();
524 DebugLoc DL = Op.getDebugLoc();
525 switch(IntrinsicID) {
526 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
527 case AMDGPUIntrinsic::R600_load_input: {
528 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
529 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
530 MachineFunction &MF = DAG.getMachineFunction();
531 MachineRegisterInfo &MRI = MF.getRegInfo();
533 return DAG.getCopyFromReg(DAG.getEntryNode(),
534 DAG.getEntryNode().getDebugLoc(), Reg, VT);
537 case AMDGPUIntrinsic::R600_interp_input: {
538 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
539 int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
540 MachineSDNode *interp;
542 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
543 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
544 return DAG.getTargetExtractSubreg(
545 TII->getRegisterInfo().getSubRegFromChannel(slot % 4),
546 DL, MVT::f32, SDValue(interp, 0));
550 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
551 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
552 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
553 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1), MVT::f32),
554 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
555 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb), MVT::f32));
557 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
558 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
559 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
560 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1), MVT::f32),
561 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
562 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb), MVT::f32));
564 return SDValue(interp, slot % 2);
566 case AMDGPUIntrinsic::R600_tex:
567 case AMDGPUIntrinsic::R600_texc:
568 case AMDGPUIntrinsic::R600_txl:
569 case AMDGPUIntrinsic::R600_txlc:
570 case AMDGPUIntrinsic::R600_txb:
571 case AMDGPUIntrinsic::R600_txbc:
572 case AMDGPUIntrinsic::R600_txf:
573 case AMDGPUIntrinsic::R600_txq:
574 case AMDGPUIntrinsic::R600_ddx:
575 case AMDGPUIntrinsic::R600_ddy: {
577 switch (IntrinsicID) {
578 case AMDGPUIntrinsic::R600_tex:
581 case AMDGPUIntrinsic::R600_texc:
584 case AMDGPUIntrinsic::R600_txl:
587 case AMDGPUIntrinsic::R600_txlc:
590 case AMDGPUIntrinsic::R600_txb:
593 case AMDGPUIntrinsic::R600_txbc:
596 case AMDGPUIntrinsic::R600_txf:
599 case AMDGPUIntrinsic::R600_txq:
602 case AMDGPUIntrinsic::R600_ddx:
605 case AMDGPUIntrinsic::R600_ddy:
609 llvm_unreachable("Unknow Texture Operation");
612 SDValue TexArgs[19] = {
613 DAG.getConstant(TextureOp, MVT::i32),
615 DAG.getConstant(0, MVT::i32),
616 DAG.getConstant(1, MVT::i32),
617 DAG.getConstant(2, MVT::i32),
618 DAG.getConstant(3, MVT::i32),
622 DAG.getConstant(0, MVT::i32),
623 DAG.getConstant(1, MVT::i32),
624 DAG.getConstant(2, MVT::i32),
625 DAG.getConstant(3, MVT::i32),
633 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs, 19);
635 case AMDGPUIntrinsic::AMDGPU_dp4: {
637 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
638 DAG.getConstant(0, MVT::i32)),
639 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
640 DAG.getConstant(0, MVT::i32)),
641 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
642 DAG.getConstant(1, MVT::i32)),
643 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
644 DAG.getConstant(1, MVT::i32)),
645 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
646 DAG.getConstant(2, MVT::i32)),
647 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
648 DAG.getConstant(2, MVT::i32)),
649 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
650 DAG.getConstant(3, MVT::i32)),
651 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
652 DAG.getConstant(3, MVT::i32))
654 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args, 8);
657 case r600_read_ngroups_x:
658 return LowerImplicitParameter(DAG, VT, DL, 0);
659 case r600_read_ngroups_y:
660 return LowerImplicitParameter(DAG, VT, DL, 1);
661 case r600_read_ngroups_z:
662 return LowerImplicitParameter(DAG, VT, DL, 2);
663 case r600_read_global_size_x:
664 return LowerImplicitParameter(DAG, VT, DL, 3);
665 case r600_read_global_size_y:
666 return LowerImplicitParameter(DAG, VT, DL, 4);
667 case r600_read_global_size_z:
668 return LowerImplicitParameter(DAG, VT, DL, 5);
669 case r600_read_local_size_x:
670 return LowerImplicitParameter(DAG, VT, DL, 6);
671 case r600_read_local_size_y:
672 return LowerImplicitParameter(DAG, VT, DL, 7);
673 case r600_read_local_size_z:
674 return LowerImplicitParameter(DAG, VT, DL, 8);
676 case r600_read_tgid_x:
677 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
679 case r600_read_tgid_y:
680 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
682 case r600_read_tgid_z:
683 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
685 case r600_read_tidig_x:
686 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
688 case r600_read_tidig_y:
689 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
691 case r600_read_tidig_z:
692 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
695 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
698 } // end switch(Op.getOpcode())
702 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
703 SmallVectorImpl<SDValue> &Results,
704 SelectionDAG &DAG) const {
705 switch (N->getOpcode()) {
707 case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
710 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
711 Results.push_back(SDValue(Node, 0));
712 Results.push_back(SDValue(Node, 1));
713 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
715 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
719 SDNode *Node = LowerSTORE(SDValue(N, 0), DAG).getNode();
720 Results.push_back(SDValue(Node, 0));
725 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
730 Op, DAG.getConstantFP(0.0f, MVT::f32),
731 DAG.getCondCode(ISD::SETNE)
735 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
737 unsigned DwordOffset) const {
738 unsigned ByteOffset = DwordOffset * 4;
739 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
740 AMDGPUAS::PARAM_I_ADDRESS);
742 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
743 assert(isInt<16>(ByteOffset));
745 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
746 DAG.getConstant(ByteOffset, MVT::i32), // PTR
747 MachinePointerInfo(ConstantPointerNull::get(PtrType)),
748 false, false, false, 0);
751 SDValue R600TargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
753 MachineFunction &MF = DAG.getMachineFunction();
754 const AMDGPUFrameLowering *TFL =
755 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
757 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op);
760 unsigned FrameIndex = FIN->getIndex();
761 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
762 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), MVT::i32);
765 bool R600TargetLowering::isZero(SDValue Op) const {
766 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
767 return Cst->isNullValue();
768 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
769 return CstFP->isZero();
775 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
776 DebugLoc DL = Op.getDebugLoc();
777 EVT VT = Op.getValueType();
779 SDValue LHS = Op.getOperand(0);
780 SDValue RHS = Op.getOperand(1);
781 SDValue True = Op.getOperand(2);
782 SDValue False = Op.getOperand(3);
783 SDValue CC = Op.getOperand(4);
786 // LHS and RHS are guaranteed to be the same value type
787 EVT CompareVT = LHS.getValueType();
789 // Check if we can lower this to a native operation.
791 // Try to lower to a SET* instruction:
793 // SET* can match the following patterns:
795 // select_cc f32, f32, -1, 0, cc_any
796 // select_cc f32, f32, 1.0f, 0.0f, cc_any
797 // select_cc i32, i32, -1, 0, cc_any
800 // Move hardware True/False values to the correct operand.
801 if (isHWTrueValue(False) && isHWFalseValue(True)) {
802 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
803 std::swap(False, True);
804 CC = DAG.getCondCode(ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32));
807 if (isHWTrueValue(True) && isHWFalseValue(False) &&
808 (CompareVT == VT || VT == MVT::i32)) {
809 // This can be matched by a SET* instruction.
810 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
813 // Try to lower to a CND* instruction:
815 // CND* can match the following patterns:
817 // select_cc f32, 0.0, f32, f32, cc_any
818 // select_cc f32, 0.0, i32, i32, cc_any
819 // select_cc i32, 0, f32, f32, cc_any
820 // select_cc i32, 0, i32, i32, cc_any
822 if (isZero(LHS) || isZero(RHS)) {
823 SDValue Cond = (isZero(LHS) ? RHS : LHS);
824 SDValue Zero = (isZero(LHS) ? LHS : RHS);
825 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
826 if (CompareVT != VT) {
827 // Bitcast True / False to the correct types. This will end up being
828 // a nop, but it allows us to define only a single pattern in the
829 // .TD files for each CND* instruction rather than having to have
830 // one pattern for integer True/False and one for fp True/False
831 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
832 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
835 CCOpcode = ISD::getSetCCSwappedOperands(CCOpcode);
848 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
856 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
859 DAG.getCondCode(CCOpcode));
860 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
864 // Possible Min/Max pattern
865 SDValue MinMax = LowerMinMax(Op, DAG);
866 if (MinMax.getNode()) {
870 // If we make it this for it means we have no native instructions to handle
871 // this SELECT_CC, so we must lower it.
872 SDValue HWTrue, HWFalse;
874 if (CompareVT == MVT::f32) {
875 HWTrue = DAG.getConstantFP(1.0f, CompareVT);
876 HWFalse = DAG.getConstantFP(0.0f, CompareVT);
877 } else if (CompareVT == MVT::i32) {
878 HWTrue = DAG.getConstant(-1, CompareVT);
879 HWFalse = DAG.getConstant(0, CompareVT);
882 assert(!"Unhandled value type in LowerSELECT_CC");
885 // Lower this unsupported SELECT_CC into a combination of two supported
886 // SELECT_CC operations.
887 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
889 return DAG.getNode(ISD::SELECT_CC, DL, VT,
892 DAG.getCondCode(ISD::SETNE));
895 SDValue R600TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
896 return DAG.getNode(ISD::SELECT_CC,
900 DAG.getConstant(0, MVT::i32),
903 DAG.getCondCode(ISD::SETNE));
906 /// LLVM generates byte-addresed pointers. For indirect addressing, we need to
907 /// convert these pointers to a register index. Each register holds
908 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
909 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
910 /// for indirect addressing.
911 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
913 SelectionDAG &DAG) const {
925 default: llvm_unreachable("Invalid stack width");
928 return DAG.getNode(ISD::SRL, Ptr.getDebugLoc(), Ptr.getValueType(), Ptr,
929 DAG.getConstant(SRLPad, MVT::i32));
932 void R600TargetLowering::getStackAddress(unsigned StackWidth,
935 unsigned &PtrIncr) const {
936 switch (StackWidth) {
947 Channel = ElemIdx % 2;
961 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
962 DebugLoc DL = Op.getDebugLoc();
963 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
964 SDValue Chain = Op.getOperand(0);
965 SDValue Value = Op.getOperand(1);
966 SDValue Ptr = Op.getOperand(2);
968 if (StoreNode->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
969 Ptr->getOpcode() != AMDGPUISD::DWORDADDR) {
970 // Convert pointer from byte address to dword address.
971 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
972 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
973 Ptr, DAG.getConstant(2, MVT::i32)));
975 if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
976 assert(!"Truncated and indexed stores not supported yet");
978 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
983 EVT ValueVT = Value.getValueType();
985 if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
989 // Lowering for indirect addressing
991 const MachineFunction &MF = DAG.getMachineFunction();
992 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
993 getTargetMachine().getFrameLowering());
994 unsigned StackWidth = TFL->getStackWidth(MF);
996 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
998 if (ValueVT.isVector()) {
999 unsigned NumElemVT = ValueVT.getVectorNumElements();
1000 EVT ElemVT = ValueVT.getVectorElementType();
1003 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1004 "vector width in load");
1006 for (unsigned i = 0; i < NumElemVT; ++i) {
1007 unsigned Channel, PtrIncr;
1008 getStackAddress(StackWidth, i, Channel, PtrIncr);
1009 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1010 DAG.getConstant(PtrIncr, MVT::i32));
1011 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
1012 Value, DAG.getConstant(i, MVT::i32));
1014 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1016 DAG.getTargetConstant(Channel, MVT::i32));
1018 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores, NumElemVT);
1020 if (ValueVT == MVT::i8) {
1021 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1023 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
1024 DAG.getTargetConstant(0, MVT::i32)); // Channel
1030 // return (512 + (kc_bank << 12)
1032 ConstantAddressBlock(unsigned AddressSpace) {
1033 switch (AddressSpace) {
1034 case AMDGPUAS::CONSTANT_BUFFER_0:
1036 case AMDGPUAS::CONSTANT_BUFFER_1:
1038 case AMDGPUAS::CONSTANT_BUFFER_2:
1039 return 512 + 4096 * 2;
1040 case AMDGPUAS::CONSTANT_BUFFER_3:
1041 return 512 + 4096 * 3;
1042 case AMDGPUAS::CONSTANT_BUFFER_4:
1043 return 512 + 4096 * 4;
1044 case AMDGPUAS::CONSTANT_BUFFER_5:
1045 return 512 + 4096 * 5;
1046 case AMDGPUAS::CONSTANT_BUFFER_6:
1047 return 512 + 4096 * 6;
1048 case AMDGPUAS::CONSTANT_BUFFER_7:
1049 return 512 + 4096 * 7;
1050 case AMDGPUAS::CONSTANT_BUFFER_8:
1051 return 512 + 4096 * 8;
1052 case AMDGPUAS::CONSTANT_BUFFER_9:
1053 return 512 + 4096 * 9;
1054 case AMDGPUAS::CONSTANT_BUFFER_10:
1055 return 512 + 4096 * 10;
1056 case AMDGPUAS::CONSTANT_BUFFER_11:
1057 return 512 + 4096 * 11;
1058 case AMDGPUAS::CONSTANT_BUFFER_12:
1059 return 512 + 4096 * 12;
1060 case AMDGPUAS::CONSTANT_BUFFER_13:
1061 return 512 + 4096 * 13;
1062 case AMDGPUAS::CONSTANT_BUFFER_14:
1063 return 512 + 4096 * 14;
1064 case AMDGPUAS::CONSTANT_BUFFER_15:
1065 return 512 + 4096 * 15;
1071 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
1073 EVT VT = Op.getValueType();
1074 DebugLoc DL = Op.getDebugLoc();
1075 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1076 SDValue Chain = Op.getOperand(0);
1077 SDValue Ptr = Op.getOperand(1);
1078 SDValue LoweredLoad;
1080 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
1081 if (ConstantBlock > -1) {
1083 if (dyn_cast<ConstantExpr>(LoadNode->getSrcValue()) ||
1084 dyn_cast<Constant>(LoadNode->getSrcValue()) ||
1085 dyn_cast<ConstantSDNode>(Ptr)) {
1087 for (unsigned i = 0; i < 4; i++) {
1088 // We want Const position encoded with the following formula :
1089 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1090 // const_index is Ptr computed by llvm using an alignment of 16.
1091 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1092 // then div by 4 at the ISel step
1093 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1094 DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
1095 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1097 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Slots, 4);
1099 // non constant ptr cant be folded, keeps it as a v4f32 load
1100 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1101 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
1102 DAG.getConstant(LoadNode->getAddressSpace() -
1103 AMDGPUAS::CONSTANT_BUFFER_0, MVT::i32)
1107 if (!VT.isVector()) {
1108 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1109 DAG.getConstant(0, MVT::i32));
1112 SDValue MergedValues[2] = {
1116 return DAG.getMergeValues(MergedValues, 2, DL);
1119 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1123 // Lowering for indirect addressing
1124 const MachineFunction &MF = DAG.getMachineFunction();
1125 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
1126 getTargetMachine().getFrameLowering());
1127 unsigned StackWidth = TFL->getStackWidth(MF);
1129 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1131 if (VT.isVector()) {
1132 unsigned NumElemVT = VT.getVectorNumElements();
1133 EVT ElemVT = VT.getVectorElementType();
1136 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1137 "vector width in load");
1139 for (unsigned i = 0; i < NumElemVT; ++i) {
1140 unsigned Channel, PtrIncr;
1141 getStackAddress(StackWidth, i, Channel, PtrIncr);
1142 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1143 DAG.getConstant(PtrIncr, MVT::i32));
1144 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
1146 DAG.getTargetConstant(Channel, MVT::i32),
1149 for (unsigned i = NumElemVT; i < 4; ++i) {
1150 Loads[i] = DAG.getUNDEF(ElemVT);
1152 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
1153 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads, 4);
1155 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
1157 DAG.getTargetConstant(0, MVT::i32), // Channel
1162 Ops[0] = LoweredLoad;
1165 return DAG.getMergeValues(Ops, 2, DL);
1168 /// XXX Only kernel functions are supported, so we can assume for now that
1169 /// every function is a kernel function, but in the future we should use
1170 /// separate calling conventions for kernel and non-kernel functions.
1171 SDValue R600TargetLowering::LowerFormalArguments(
1173 CallingConv::ID CallConv,
1175 const SmallVectorImpl<ISD::InputArg> &Ins,
1176 DebugLoc DL, SelectionDAG &DAG,
1177 SmallVectorImpl<SDValue> &InVals) const {
1178 unsigned ParamOffsetBytes = 36;
1179 Function::const_arg_iterator FuncArg =
1180 DAG.getMachineFunction().getFunction()->arg_begin();
1181 for (unsigned i = 0, e = Ins.size(); i < e; ++i, ++FuncArg) {
1183 Type *ArgType = FuncArg->getType();
1184 unsigned ArgSizeInBits = ArgType->isPointerTy() ?
1185 32 : ArgType->getPrimitiveSizeInBits();
1186 unsigned ArgBytes = ArgSizeInBits >> 3;
1188 if (ArgSizeInBits < VT.getSizeInBits()) {
1189 assert(!ArgType->isFloatTy() &&
1190 "Extending floating point arguments not supported yet");
1191 ArgVT = MVT::getIntegerVT(ArgSizeInBits);
1195 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1196 AMDGPUAS::PARAM_I_ADDRESS);
1197 SDValue Arg = DAG.getExtLoad(ISD::ZEXTLOAD, DL, VT, DAG.getRoot(),
1198 DAG.getConstant(ParamOffsetBytes, MVT::i32),
1199 MachinePointerInfo(UndefValue::get(PtrTy)),
1200 ArgVT, false, false, ArgBytes);
1201 InVals.push_back(Arg);
1202 ParamOffsetBytes += ArgBytes;
1207 EVT R600TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1208 if (!VT.isVector()) return MVT::i32;
1209 return VT.changeVectorElementTypeToInteger();
1212 //===----------------------------------------------------------------------===//
1213 // Custom DAG Optimizations
1214 //===----------------------------------------------------------------------===//
1216 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1217 DAGCombinerInfo &DCI) const {
1218 SelectionDAG &DAG = DCI.DAG;
1220 switch (N->getOpcode()) {
1221 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1222 case ISD::FP_ROUND: {
1223 SDValue Arg = N->getOperand(0);
1224 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1225 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), N->getValueType(0),
1231 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1232 // (i32 select_cc f32, f32, -1, 0 cc)
1234 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1235 // this to one of the SET*_DX10 instructions.
1236 case ISD::FP_TO_SINT: {
1237 SDValue FNeg = N->getOperand(0);
1238 if (FNeg.getOpcode() != ISD::FNEG) {
1241 SDValue SelectCC = FNeg.getOperand(0);
1242 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1243 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1244 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1245 !isHWTrueValue(SelectCC.getOperand(2)) ||
1246 !isHWFalseValue(SelectCC.getOperand(3))) {
1250 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N->getValueType(0),
1251 SelectCC.getOperand(0), // LHS
1252 SelectCC.getOperand(1), // RHS
1253 DAG.getConstant(-1, MVT::i32), // True
1254 DAG.getConstant(0, MVT::i32), // Flase
1255 SelectCC.getOperand(4)); // CC
1259 // Extract_vec (Build_vector) generated by custom lowering
1260 // also needs to be customly combined
1261 case ISD::EXTRACT_VECTOR_ELT: {
1262 SDValue Arg = N->getOperand(0);
1263 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1264 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1265 unsigned Element = Const->getZExtValue();
1266 return Arg->getOperand(Element);
1269 if (Arg.getOpcode() == ISD::BITCAST &&
1270 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1271 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1272 unsigned Element = Const->getZExtValue();
1273 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getVTList(),
1274 Arg->getOperand(0).getOperand(Element));
1279 case ISD::SELECT_CC: {
1280 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1281 // selectcc x, y, a, b, inv(cc)
1283 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1284 // selectcc x, y, a, b, cc
1285 SDValue LHS = N->getOperand(0);
1286 if (LHS.getOpcode() != ISD::SELECT_CC) {
1290 SDValue RHS = N->getOperand(1);
1291 SDValue True = N->getOperand(2);
1292 SDValue False = N->getOperand(3);
1293 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1295 if (LHS.getOperand(2).getNode() != True.getNode() ||
1296 LHS.getOperand(3).getNode() != False.getNode() ||
1297 RHS.getNode() != False.getNode()) {
1302 default: return SDValue();
1303 case ISD::SETNE: return LHS;
1305 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1306 LHSCC = ISD::getSetCCInverse(LHSCC,
1307 LHS.getOperand(0).getValueType().isInteger());
1308 return DAG.getSelectCC(N->getDebugLoc(),
1317 case AMDGPUISD::EXPORT: {
1318 SDValue Arg = N->getOperand(1);
1319 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1321 SDValue NewBldVec[4] = {
1322 DAG.getUNDEF(MVT::f32),
1323 DAG.getUNDEF(MVT::f32),
1324 DAG.getUNDEF(MVT::f32),
1325 DAG.getUNDEF(MVT::f32)
1327 SDValue NewArgs[8] = {
1328 N->getOperand(0), // Chain
1330 N->getOperand(2), // ArrayBase
1331 N->getOperand(3), // Type
1332 N->getOperand(4), // SWZ_X
1333 N->getOperand(5), // SWZ_Y
1334 N->getOperand(6), // SWZ_Z
1335 N->getOperand(7) // SWZ_W
1337 for (unsigned i = 0; i < Arg.getNumOperands(); i++) {
1338 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Arg.getOperand(i))) {
1340 NewArgs[4 + i] = DAG.getConstant(4, MVT::i32); // SEL_0
1341 } else if (C->isExactlyValue(1.0)) {
1342 NewArgs[4 + i] = DAG.getConstant(5, MVT::i32); // SEL_0
1344 NewBldVec[i] = Arg.getOperand(i);
1347 NewBldVec[i] = Arg.getOperand(i);
1350 DebugLoc DL = N->getDebugLoc();
1351 NewArgs[1] = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4f32, NewBldVec, 4);
1352 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs, 8);