1 //===-- R600EmitClauseMarkers.cpp - Emit CF_ALU ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// Add CF_ALU. R600 Alu instructions are grouped in clause which can hold
12 /// 128 Alu instructions ; these instructions can access up to 4 prefetched
13 /// 4 lines of 16 registers from constant buffers. Such ALU clauses are
14 /// initiated by CF_ALU instructions.
15 //===----------------------------------------------------------------------===//
18 #include "R600Defines.h"
19 #include "R600InstrInfo.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 class R600EmitClauseMarkersPass : public MachineFunctionPass {
32 const R600InstrInfo *TII;
34 unsigned OccupiedDwords(MachineInstr *MI) const {
35 switch (MI->getOpcode()) {
36 case AMDGPU::INTERP_PAIR_XY:
37 case AMDGPU::INTERP_PAIR_ZW:
38 case AMDGPU::INTERP_VEC_LOAD:
47 if(TII->isVector(*MI) ||
48 TII->isCubeOp(MI->getOpcode()) ||
49 TII->isReductionOp(MI->getOpcode()))
52 unsigned NumLiteral = 0;
53 for (MachineInstr::mop_iterator It = MI->operands_begin(),
54 E = MI->operands_end(); It != E; ++It) {
55 MachineOperand &MO = *It;
56 if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
59 return 1 + NumLiteral;
62 bool isALU(const MachineInstr *MI) const {
63 if (TII->isALUInstr(MI->getOpcode()))
65 if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode()))
67 switch (MI->getOpcode()) {
69 case AMDGPU::INTERP_PAIR_XY:
70 case AMDGPU::INTERP_PAIR_ZW:
71 case AMDGPU::INTERP_VEC_LOAD:
80 bool IsTrivialInst(MachineInstr *MI) const {
81 switch (MI->getOpcode()) {
90 std::pair<unsigned, unsigned> getAccessedBankLine(unsigned Sel) const {
91 // Sel is (512 + (kc_bank << 12) + ConstIndex) << 2
92 // (See also R600ISelLowering.cpp)
93 // ConstIndex value is in [0, 4095];
94 return std::pair<unsigned, unsigned>(
95 ((Sel >> 2) - 512) >> 12, // KC_BANK
96 // Line Number of ConstIndex
97 // A line contains 16 constant registers however KCX bank can lock
98 // two line at the same time ; thus we want to get an even line number.
99 // Line number can be retrieved with (>>4), using (>>5) <<1 generates
101 ((((Sel >> 2) - 512) & 4095) >> 5) << 1);
104 bool SubstituteKCacheBank(MachineInstr *MI,
105 std::vector<std::pair<unsigned, unsigned> > &CachedConsts) const {
106 std::vector<std::pair<unsigned, unsigned> > UsedKCache;
107 const SmallVector<std::pair<MachineOperand *, int64_t>, 3> &Consts =
109 assert(TII->isALUInstr(MI->getOpcode()) && "Can't assign Const");
110 for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
111 if (Consts[i].first->getReg() != AMDGPU::ALU_CONST)
113 unsigned Sel = Consts[i].second;
114 unsigned Chan = Sel & 3, Index = ((Sel >> 2) - 512) & 31;
115 unsigned KCacheIndex = Index * 4 + Chan;
116 const std::pair<unsigned, unsigned> &BankLine = getAccessedBankLine(Sel);
117 if (CachedConsts.empty()) {
118 CachedConsts.push_back(BankLine);
119 UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
122 if (CachedConsts[0] == BankLine) {
123 UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
126 if (CachedConsts.size() == 1) {
127 CachedConsts.push_back(BankLine);
128 UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
131 if (CachedConsts[1] == BankLine) {
132 UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
138 for (unsigned i = 0, j = 0, n = Consts.size(); i < n; ++i) {
139 if (Consts[i].first->getReg() != AMDGPU::ALU_CONST)
141 switch(UsedKCache[j].first) {
143 Consts[i].first->setReg(
144 AMDGPU::R600_KC0RegClass.getRegister(UsedKCache[j].second));
147 Consts[i].first->setReg(
148 AMDGPU::R600_KC1RegClass.getRegister(UsedKCache[j].second));
151 llvm_unreachable("Wrong Cache Line");
158 MachineBasicBlock::iterator
159 MakeALUClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const {
160 MachineBasicBlock::iterator ClauseHead = I;
161 std::vector<std::pair<unsigned, unsigned> > KCacheBanks;
162 bool PushBeforeModifier = false;
163 unsigned AluInstCount = 0;
164 for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
165 if (IsTrivialInst(I))
169 if (AluInstCount > TII->getMaxAlusPerClause())
171 if (I->getOpcode() == AMDGPU::PRED_X) {
172 if (TII->getFlagOp(I).getImm() & MO_FLAG_PUSH)
173 PushBeforeModifier = true;
177 if (I->getOpcode() == AMDGPU::KILLGT) {
181 if (TII->isALUInstr(I->getOpcode()) &&
182 !SubstituteKCacheBank(I, KCacheBanks))
184 AluInstCount += OccupiedDwords(I);
186 unsigned Opcode = PushBeforeModifier ?
187 AMDGPU::CF_ALU_PUSH_BEFORE : AMDGPU::CF_ALU;
188 BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), TII->get(Opcode))
190 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].first) // KB0
191 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].first) // KB1
192 .addImm(KCacheBanks.empty()?0:2) // KM0
193 .addImm((KCacheBanks.size() < 2)?0:2) // KM1
194 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].second) // KLINE0
195 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].second) // KLINE1
196 .addImm(AluInstCount); // COUNT
201 R600EmitClauseMarkersPass(TargetMachine &tm) : MachineFunctionPass(ID),
202 TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) { }
204 virtual bool runOnMachineFunction(MachineFunction &MF) {
205 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
207 MachineBasicBlock &MBB = *BB;
208 MachineBasicBlock::iterator I = MBB.begin();
209 if (I->getOpcode() == AMDGPU::CF_ALU)
210 continue; // BB was already parsed
211 for (MachineBasicBlock::iterator E = MBB.end(); I != E;) {
213 I = MakeALUClause(MBB, I);
221 const char *getPassName() const {
222 return "R600 Emit Clause Markers Pass";
226 char R600EmitClauseMarkersPass::ID = 0;
231 llvm::FunctionPass *llvm::createR600EmitClauseMarkers(TargetMachine &TM) {
232 return new R600EmitClauseMarkersPass(TM);