1 //===-- SIMCCodeEmitter.cpp - SI Code Emitter -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief The SI code emitter produces machine code that can be executed
12 /// directly on the GPU device.
14 //===----------------------------------------------------------------------===//
16 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
17 #include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCFixup.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/raw_ostream.h"
27 #define VGPR_BIT(src_idx) (1ULL << (9 * src_idx - 1))
28 #define SI_INSTR_FLAGS_ENCODING_MASK 0xf
30 // These must be kept in sync with SIInstructions.td and also the
31 // InstrEncodingInfo array in SIInstrInfo.cpp.
33 // NOTE: This enum is only used to identify the encoding type within LLVM,
34 // the actual encoding type that is part of the instruction format is different
35 namespace SIInstrEncodingType {
59 class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
60 SIMCCodeEmitter(const SIMCCodeEmitter &); // DO NOT IMPLEMENT
61 void operator=(const SIMCCodeEmitter &); // DO NOT IMPLEMENT
62 const MCInstrInfo &MCII;
63 const MCRegisterInfo &MRI;
64 const MCSubtargetInfo &STI;
68 SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
69 const MCSubtargetInfo &sti, MCContext &ctx)
70 : MCII(mcii), MRI(mri), STI(sti), Ctx(ctx) { }
72 ~SIMCCodeEmitter() { }
74 /// \breif Encode the instruction and write it to the OS.
75 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
76 SmallVectorImpl<MCFixup> &Fixups) const;
78 /// \returns the encoding for an MCOperand.
79 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
80 SmallVectorImpl<MCFixup> &Fixups) const;
84 /// \brief Encode a sequence of registers with the correct alignment.
85 unsigned GPRAlign(const MCInst &MI, unsigned OpNo, unsigned shift) const;
87 /// \brief Encoding for when 2 consecutive registers are used
88 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo,
89 SmallVectorImpl<MCFixup> &Fixup) const;
91 /// \brief Encoding for when 4 consectuive registers are used
92 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo,
93 SmallVectorImpl<MCFixup> &Fixup) const;
95 /// \brief Encoding for SMRD indexed loads
96 virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo,
97 SmallVectorImpl<MCFixup> &Fixup) const;
99 /// \brief Post-Encoder method for VOP instructions
100 virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const;
104 /// \returns this SIInstrEncodingType for this instruction.
105 unsigned getEncodingType(const MCInst &MI) const;
107 /// \brief Get then size in bytes of this instructions encoding.
108 unsigned getEncodingBytes(const MCInst &MI) const;
110 /// \returns the hardware encoding for a register
111 unsigned getRegBinaryCode(unsigned reg) const;
113 /// \brief Generated function that returns the hardware encoding for
115 unsigned getHWRegNum(unsigned reg) const;
119 } // End anonymous namespace
121 MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
122 const MCRegisterInfo &MRI,
123 const MCSubtargetInfo &STI,
125 return new SIMCCodeEmitter(MCII, MRI, STI, Ctx);
128 void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
129 SmallVectorImpl<MCFixup> &Fixups) const {
130 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups);
131 unsigned bytes = getEncodingBytes(MI);
132 for (unsigned i = 0; i < bytes; i++) {
133 OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
137 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
139 SmallVectorImpl<MCFixup> &Fixups) const {
141 return getRegBinaryCode(MO.getReg());
142 } else if (MO.isImm()) {
144 } else if (MO.isFPImm()) {
145 // XXX: Not all instructions can use inline literals
146 // XXX: We should make sure this is a 32-bit constant
151 Imm.F = MO.getFPImm();
153 } else if (MO.isExpr()) {
154 const MCExpr *Expr = MO.getExpr();
155 MCFixupKind Kind = MCFixupKind(FK_PCRel_4);
156 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
159 llvm_unreachable("Encoding of this operand type is not supported yet.");
164 //===----------------------------------------------------------------------===//
165 // Custom Operand Encodings
166 //===----------------------------------------------------------------------===//
168 unsigned SIMCCodeEmitter::GPRAlign(const MCInst &MI, unsigned OpNo,
169 unsigned shift) const {
170 unsigned regCode = getRegBinaryCode(MI.getOperand(OpNo).getReg());
171 return regCode >> shift;
174 unsigned SIMCCodeEmitter::GPR2AlignEncode(const MCInst &MI,
176 SmallVectorImpl<MCFixup> &Fixup) const {
177 return GPRAlign(MI, OpNo, 1);
180 unsigned SIMCCodeEmitter::GPR4AlignEncode(const MCInst &MI,
182 SmallVectorImpl<MCFixup> &Fixup) const {
183 return GPRAlign(MI, OpNo, 2);
186 #define SMRD_OFFSET_MASK 0xff
187 #define SMRD_IMM_SHIFT 8
188 #define SMRD_SBASE_MASK 0x3f
189 #define SMRD_SBASE_SHIFT 9
190 /// This function is responsibe for encoding the offset
191 /// and the base ptr for SMRD instructions it should return a bit string in
194 /// OFFSET = bits{7-0}
196 /// SBASE = bits{14-9}
198 uint32_t SIMCCodeEmitter::SMRDmemriEncode(const MCInst &MI, unsigned OpNo,
199 SmallVectorImpl<MCFixup> &Fixup) const {
202 const MCOperand &OffsetOp = MI.getOperand(OpNo + 1);
204 //XXX: Use this function for SMRD loads with register offsets
205 assert(OffsetOp.isImm());
208 (getMachineOpValue(MI, OffsetOp, Fixup) & SMRD_OFFSET_MASK)
209 | (1 << SMRD_IMM_SHIFT) //XXX If the Offset is a register we shouldn't set this bit
210 | ((GPR2AlignEncode(MI, OpNo, Fixup) & SMRD_SBASE_MASK) << SMRD_SBASE_SHIFT)
216 //===----------------------------------------------------------------------===//
217 // Post Encoder Callbacks
218 //===----------------------------------------------------------------------===//
220 uint64_t SIMCCodeEmitter::VOPPostEncode(const MCInst &MI, uint64_t Value) const{
221 unsigned encodingType = getEncodingType(MI);
223 unsigned vgprBitOffset;
225 if (encodingType == SIInstrEncodingType::VOP3) {
233 // Add one to skip over the destination reg operand.
234 for (unsigned opIdx = 1; opIdx < numSrcOps + 1; opIdx++) {
235 const MCOperand &MO = MI.getOperand(opIdx);
237 unsigned reg = MI.getOperand(opIdx).getReg();
238 if (AMDGPUMCRegisterClasses[AMDGPU::VReg_32RegClassID].contains(reg) ||
239 AMDGPUMCRegisterClasses[AMDGPU::VReg_64RegClassID].contains(reg)) {
240 Value |= (VGPR_BIT(opIdx)) << vgprBitOffset;
242 } else if (MO.isFPImm()) {
247 // XXX: Not all instructions can use inline literals
248 // XXX: We should make sure this is a 32-bit constant
249 Imm.f = MO.getFPImm();
250 Value |= ((uint64_t)Imm.i) << 32;
256 //===----------------------------------------------------------------------===//
257 // Encoding helper functions
258 //===----------------------------------------------------------------------===//
260 unsigned SIMCCodeEmitter::getEncodingType(const MCInst &MI) const {
261 return MCII.get(MI.getOpcode()).TSFlags & SI_INSTR_FLAGS_ENCODING_MASK;
264 unsigned SIMCCodeEmitter::getEncodingBytes(const MCInst &MI) const {
266 // These instructions aren't real instructions with an encoding type, so
267 // we need to manually specify their size.
268 switch (MI.getOpcode()) {
270 case AMDGPU::SI_LOAD_LITERAL_I32:
271 case AMDGPU::SI_LOAD_LITERAL_F32:
275 unsigned encoding_type = getEncodingType(MI);
276 switch (encoding_type) {
277 case SIInstrEncodingType::EXP:
278 case SIInstrEncodingType::LDS:
279 case SIInstrEncodingType::MUBUF:
280 case SIInstrEncodingType::MTBUF:
281 case SIInstrEncodingType::MIMG:
282 case SIInstrEncodingType::VOP3:
290 unsigned SIMCCodeEmitter::getRegBinaryCode(unsigned reg) const {
292 case AMDGPU::M0: return 124;
293 case AMDGPU::SREG_LIT_0: return 128;
294 case AMDGPU::SI_LITERAL_CONSTANT: return 255;
295 default: return MRI.getEncodingValue(reg);