1 //===-- SIMCCodeEmitter.cpp - SI Code Emitter -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief The SI code emitter produces machine code that can be executed
12 /// directly on the GPU device.
14 //===----------------------------------------------------------------------===//
16 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
17 #include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCFixup.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/raw_ostream.h"
31 /// \brief Helper type used in encoding
37 class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
38 SIMCCodeEmitter(const SIMCCodeEmitter &) LLVM_DELETED_FUNCTION;
39 void operator=(const SIMCCodeEmitter &) LLVM_DELETED_FUNCTION;
40 const MCInstrInfo &MCII;
41 const MCRegisterInfo &MRI;
43 /// \brief Can this operand also contain immediate values?
44 bool isSrcOperand(const MCInstrDesc &Desc, unsigned OpNo) const;
46 /// \brief Encode an fp or int literal
47 uint32_t getLitEncoding(const MCOperand &MO) const;
50 SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
51 const MCSubtargetInfo &sti, MCContext &ctx)
52 : MCII(mcii), MRI(mri) { }
54 ~SIMCCodeEmitter() { }
56 /// \brief Encode the instruction and write it to the OS.
57 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
58 SmallVectorImpl<MCFixup> &Fixups,
59 const MCSubtargetInfo &STI) const;
61 /// \returns the encoding for an MCOperand.
62 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
63 SmallVectorImpl<MCFixup> &Fixups) const;
66 } // End anonymous namespace
68 MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
69 const MCRegisterInfo &MRI,
70 const MCSubtargetInfo &STI,
72 return new SIMCCodeEmitter(MCII, MRI, STI, Ctx);
75 bool SIMCCodeEmitter::isSrcOperand(const MCInstrDesc &Desc,
76 unsigned OpNo) const {
78 unsigned RegClass = Desc.OpInfo[OpNo].RegClass;
79 return (AMDGPU::SSrc_32RegClassID == RegClass) ||
80 (AMDGPU::SSrc_64RegClassID == RegClass) ||
81 (AMDGPU::VSrc_32RegClassID == RegClass) ||
82 (AMDGPU::VSrc_64RegClassID == RegClass);
85 uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO) const {
90 else if (MO.isFPImm())
91 Imm.F = MO.getFPImm();
95 if (Imm.I >= 0 && Imm.I <= 64)
98 if (Imm.I >= -16 && Imm.I <= -1)
99 return 192 + abs(Imm.I);
128 void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
129 SmallVectorImpl<MCFixup> &Fixups,
130 const MCSubtargetInfo &STI) const {
132 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups);
133 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
134 unsigned bytes = Desc.getSize();
136 for (unsigned i = 0; i < bytes; i++) {
137 OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
143 // Check for additional literals in SRC0/1/2 (Op 1/2/3)
144 for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {
146 // Check if this operand should be encoded as [SV]Src
147 if (!isSrcOperand(Desc, i))
150 // Is this operand a literal immediate?
151 const MCOperand &Op = MI.getOperand(i);
152 if (getLitEncoding(Op) != 255)
160 Imm.F = Op.getFPImm();
162 for (unsigned j = 0; j < 4; j++) {
163 OS.write((uint8_t) ((Imm.I >> (8 * j)) & 0xff));
166 // Only one literal value allowed
171 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
173 SmallVectorImpl<MCFixup> &Fixups) const {
175 return MRI.getEncodingValue(MO.getReg());
178 const MCExpr *Expr = MO.getExpr();
179 MCFixupKind Kind = MCFixupKind(FK_PCRel_4);
180 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
184 // Figure out the operand number, needed for isSrcOperand check
186 for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) {
187 if (&MO == &MI.getOperand(OpNo))
191 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
192 if (isSrcOperand(Desc, OpNo)) {
193 uint32_t Enc = getLitEncoding(MO);
194 if (Enc != ~0U && (Enc != 255 || Desc.getSize() == 4))
197 } else if (MO.isImm())
200 llvm_unreachable("Encoding of this operand type is not supported yet.");