1 //===-- SIMCCodeEmitter.cpp - SI Code Emitter -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief The SI code emitter produces machine code that can be executed
12 /// directly on the GPU device.
14 //===----------------------------------------------------------------------===//
16 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
17 #include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCFixup.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/raw_ostream.h"
31 /// \brief Helper type used in encoding
37 class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
38 SIMCCodeEmitter(const SIMCCodeEmitter &); // DO NOT IMPLEMENT
39 void operator=(const SIMCCodeEmitter &); // DO NOT IMPLEMENT
40 const MCInstrInfo &MCII;
41 const MCRegisterInfo &MRI;
42 const MCSubtargetInfo &STI;
45 /// \brief Encode a sequence of registers with the correct alignment.
46 unsigned GPRAlign(const MCInst &MI, unsigned OpNo, unsigned shift) const;
48 /// \brief Can this operand also contain immediate values?
49 bool isSrcOperand(const MCInstrDesc &Desc, unsigned OpNo) const;
51 /// \brief Encode an fp or int literal
52 uint32_t getLitEncoding(const MCOperand &MO) const;
55 SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
56 const MCSubtargetInfo &sti, MCContext &ctx)
57 : MCII(mcii), MRI(mri), STI(sti), Ctx(ctx) { }
59 ~SIMCCodeEmitter() { }
61 /// \breif Encode the instruction and write it to the OS.
62 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
63 SmallVectorImpl<MCFixup> &Fixups) const;
65 /// \returns the encoding for an MCOperand.
66 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
67 SmallVectorImpl<MCFixup> &Fixups) const;
69 /// \brief Encoding for when 2 consecutive registers are used
70 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo,
71 SmallVectorImpl<MCFixup> &Fixup) const;
73 /// \brief Encoding for when 4 consectuive registers are used
74 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo,
75 SmallVectorImpl<MCFixup> &Fixup) const;
78 } // End anonymous namespace
80 MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
81 const MCRegisterInfo &MRI,
82 const MCSubtargetInfo &STI,
84 return new SIMCCodeEmitter(MCII, MRI, STI, Ctx);
87 bool SIMCCodeEmitter::isSrcOperand(const MCInstrDesc &Desc,
88 unsigned OpNo) const {
90 unsigned RegClass = Desc.OpInfo[OpNo].RegClass;
91 return (AMDGPU::SSrc_32RegClassID == RegClass) ||
92 (AMDGPU::SSrc_64RegClassID == RegClass) ||
93 (AMDGPU::VSrc_32RegClassID == RegClass) ||
94 (AMDGPU::VSrc_64RegClassID == RegClass);
97 uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO) const {
102 else if (MO.isFPImm())
103 Imm.F = MO.getFPImm();
107 if (Imm.I >= 0 && Imm.I <= 64)
110 if (Imm.I >= -16 && Imm.I <= -1)
111 return 192 + abs(Imm.I);
140 void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
141 SmallVectorImpl<MCFixup> &Fixups) const {
143 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups);
144 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
145 unsigned bytes = Desc.getSize();
147 for (unsigned i = 0; i < bytes; i++) {
148 OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
154 // Check for additional literals in SRC0/1/2 (Op 1/2/3)
155 for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {
157 // Check if this operand should be encoded as [SV]Src
158 if (!isSrcOperand(Desc, i))
161 // Is this operand a literal immediate?
162 const MCOperand &Op = MI.getOperand(i);
163 if (getLitEncoding(Op) != 255)
171 Imm.F = Op.getFPImm();
173 for (unsigned j = 0; j < 4; j++) {
174 OS.write((uint8_t) ((Imm.I >> (8 * j)) & 0xff));
177 // Only one literal value allowed
182 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
184 SmallVectorImpl<MCFixup> &Fixups) const {
186 return MRI.getEncodingValue(MO.getReg());
189 const MCExpr *Expr = MO.getExpr();
190 MCFixupKind Kind = MCFixupKind(FK_PCRel_4);
191 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
195 // Figure out the operand number, needed for isSrcOperand check
197 for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) {
198 if (&MO == &MI.getOperand(OpNo))
202 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
203 if (isSrcOperand(Desc, OpNo)) {
204 uint32_t Enc = getLitEncoding(MO);
205 if (Enc != ~0U && (Enc != 255 || Desc.getSize() == 4))
208 } else if (MO.isImm())
211 llvm_unreachable("Encoding of this operand type is not supported yet.");
215 //===----------------------------------------------------------------------===//
216 // Custom Operand Encodings
217 //===----------------------------------------------------------------------===//
219 unsigned SIMCCodeEmitter::GPRAlign(const MCInst &MI, unsigned OpNo,
220 unsigned shift) const {
221 unsigned regCode = MRI.getEncodingValue(MI.getOperand(OpNo).getReg());
222 return (regCode & 0xff) >> shift;
225 unsigned SIMCCodeEmitter::GPR2AlignEncode(const MCInst &MI,
227 SmallVectorImpl<MCFixup> &Fixup) const {
228 return GPRAlign(MI, OpNo, 1);
231 unsigned SIMCCodeEmitter::GPR4AlignEncode(const MCInst &MI,
233 SmallVectorImpl<MCFixup> &Fixup) const {
234 return GPRAlign(MI, OpNo, 2);