1 //===- R600MCCodeEmitter.cpp - Code Emitter for R600->Cayman GPU families -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 /// This code emitter outputs bytecode that is understood by the r600g driver
13 /// in the Mesa [1] project. The bytecode is very similar to the hardware's ISA,
14 /// but it still needs to be run through a finalizer in order to be executed
17 /// [1] http://www.mesa3d.org/
19 //===----------------------------------------------------------------------===//
21 #include "R600Defines.h"
22 #include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
23 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
24 #include "llvm/MC/MCCodeEmitter.h"
25 #include "llvm/MC/MCContext.h"
26 #include "llvm/MC/MCInst.h"
27 #include "llvm/MC/MCInstrInfo.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/MC/MCSubtargetInfo.h"
30 #include "llvm/Support/raw_ostream.h"
33 #define SRC_BYTE_COUNT 11
34 #define DST_BYTE_COUNT 5
40 class R600MCCodeEmitter : public AMDGPUMCCodeEmitter {
41 R600MCCodeEmitter(const R600MCCodeEmitter &); // DO NOT IMPLEMENT
42 void operator=(const R600MCCodeEmitter &); // DO NOT IMPLEMENT
43 const MCInstrInfo &MCII;
44 const MCRegisterInfo &MRI;
45 const MCSubtargetInfo &STI;
50 R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
51 const MCSubtargetInfo &sti, MCContext &ctx)
52 : MCII(mcii), MRI(mri), STI(sti), Ctx(ctx) { }
54 /// \brief Encode the instruction and write it to the OS.
55 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
56 SmallVectorImpl<MCFixup> &Fixups) const;
58 /// \returns the encoding for an MCOperand.
59 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
60 SmallVectorImpl<MCFixup> &Fixups) const;
63 void EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
64 raw_ostream &OS) const;
65 void EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const;
66 void EmitSrcISA(const MCInst &MI, unsigned RegOpIdx, unsigned SelOpIdx,
67 raw_ostream &OS) const;
68 void EmitDst(const MCInst &MI, raw_ostream &OS) const;
69 void EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
70 raw_ostream &OS) const;
71 void EmitFCInstr(const MCInst &MI, raw_ostream &OS) const;
73 void EmitNullBytes(unsigned int byteCount, raw_ostream &OS) const;
75 void EmitByte(unsigned int byte, raw_ostream &OS) const;
77 void EmitTwoBytes(uint32_t bytes, raw_ostream &OS) const;
79 void Emit(uint32_t value, raw_ostream &OS) const;
80 void Emit(uint64_t value, raw_ostream &OS) const;
82 unsigned getHWRegChan(unsigned reg) const;
83 unsigned getHWReg(unsigned regNo) const;
85 bool isFCOp(unsigned opcode) const;
86 bool isTexOp(unsigned opcode) const;
87 bool isFlagSet(const MCInst &MI, unsigned Operand, unsigned Flag) const;
91 } // End anonymous namespace
130 TEXTURE_SHADOW1D_ARRAY,
131 TEXTURE_SHADOW2D_ARRAY
134 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
135 const MCRegisterInfo &MRI,
136 const MCSubtargetInfo &STI,
138 return new R600MCCodeEmitter(MCII, MRI, STI, Ctx);
141 void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
142 SmallVectorImpl<MCFixup> &Fixups) const {
143 if (isTexOp(MI.getOpcode())) {
144 EmitTexInstr(MI, Fixups, OS);
145 } else if (isFCOp(MI.getOpcode())){
147 } else if (MI.getOpcode() == AMDGPU::RETURN ||
148 MI.getOpcode() == AMDGPU::BUNDLE ||
149 MI.getOpcode() == AMDGPU::KILL) {
152 switch(MI.getOpcode()) {
153 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
154 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
155 uint64_t inst = getBinaryCodeForInstr(MI, Fixups);
156 EmitByte(INSTR_NATIVE, OS);
160 case AMDGPU::CONSTANT_LOAD_eg:
161 case AMDGPU::VTX_READ_PARAM_8_eg:
162 case AMDGPU::VTX_READ_PARAM_16_eg:
163 case AMDGPU::VTX_READ_PARAM_32_eg:
164 case AMDGPU::VTX_READ_GLOBAL_8_eg:
165 case AMDGPU::VTX_READ_GLOBAL_32_eg:
166 case AMDGPU::VTX_READ_GLOBAL_128_eg:
167 case AMDGPU::TEX_VTX_CONSTBUF: {
168 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups);
169 uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
171 EmitByte(INSTR_VTX, OS);
172 Emit(InstWord01, OS);
176 case AMDGPU::EG_ExportSwz:
177 case AMDGPU::R600_ExportSwz:
178 case AMDGPU::EG_ExportBuf:
179 case AMDGPU::R600_ExportBuf: {
180 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups);
181 EmitByte(INSTR_EXPORT, OS);
187 EmitALUInstr(MI, Fixups, OS);
193 void R600MCCodeEmitter::EmitALUInstr(const MCInst &MI,
194 SmallVectorImpl<MCFixup> &Fixups,
195 raw_ostream &OS) const {
196 const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode());
198 // Emit instruction type
199 EmitByte(INSTR_ALU, OS);
201 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups);
203 //older alu have different encoding for instructions with one or two src
205 if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
206 !(MCDesc.TSFlags & R600_InstFlag::OP3)) {
207 uint64_t ISAOpCode = InstWord01 & (0x3FFULL << 39);
208 InstWord01 &= ~(0x3FFULL << 39);
209 InstWord01 |= ISAOpCode << 1;
212 unsigned SrcNum = MCDesc.TSFlags & R600_InstFlag::OP3 ? 3 :
213 MCDesc.TSFlags & R600_InstFlag::OP2 ? 2 : 1;
215 EmitByte(SrcNum, OS);
217 const unsigned SrcOps[3][2] = {
218 {R600Operands::SRC0, R600Operands::SRC0_SEL},
219 {R600Operands::SRC1, R600Operands::SRC1_SEL},
220 {R600Operands::SRC2, R600Operands::SRC2_SEL}
223 for (unsigned SrcIdx = 0; SrcIdx < SrcNum; ++SrcIdx) {
224 unsigned RegOpIdx = R600Operands::ALUOpTable[SrcNum-1][SrcOps[SrcIdx][0]];
225 unsigned SelOpIdx = R600Operands::ALUOpTable[SrcNum-1][SrcOps[SrcIdx][1]];
226 EmitSrcISA(MI, RegOpIdx, SelOpIdx, OS);
229 Emit(InstWord01, OS);
233 void R600MCCodeEmitter::EmitSrc(const MCInst &MI, unsigned OpIdx,
234 raw_ostream &OS) const {
235 const MCOperand &MO = MI.getOperand(OpIdx);
241 // Emit the source select (2 bytes). For GPRs, this is the register index.
242 // For other potential instruction operands, (e.g. constant registers) the
243 // value of the source select is defined in the r600isa docs.
245 unsigned reg = MO.getReg();
246 EmitTwoBytes(getHWReg(reg), OS);
247 if (reg == AMDGPU::ALU_LITERAL_X) {
248 unsigned ImmOpIndex = MI.getNumOperands() - 1;
249 MCOperand ImmOp = MI.getOperand(ImmOpIndex);
250 if (ImmOp.isFPImm()) {
251 Value.f = ImmOp.getFPImm();
253 assert(ImmOp.isImm());
254 Value.i = ImmOp.getImm();
258 // XXX: Handle other operand types.
262 // Emit the source channel (1 byte)
264 EmitByte(getHWRegChan(MO.getReg()), OS);
269 // XXX: Emit isNegated (1 byte)
270 if ((!(isFlagSet(MI, OpIdx, MO_FLAG_ABS)))
271 && (isFlagSet(MI, OpIdx, MO_FLAG_NEG) ||
273 (MO.getReg() == AMDGPU::NEG_ONE || MO.getReg() == AMDGPU::NEG_HALF)))){
279 // Emit isAbsolute (1 byte)
280 if (isFlagSet(MI, OpIdx, MO_FLAG_ABS)) {
286 // XXX: Emit relative addressing mode (1 byte)
289 // Emit kc_bank, This will be adjusted later by r600_asm
292 // Emit the literal value, if applicable (4 bytes).
297 void R600MCCodeEmitter::EmitSrcISA(const MCInst &MI, unsigned RegOpIdx,
298 unsigned SelOpIdx, raw_ostream &OS) const {
299 const MCOperand &RegMO = MI.getOperand(RegOpIdx);
300 const MCOperand &SelMO = MI.getOperand(SelOpIdx);
306 InlineConstant.i = 0;
307 // Emit source type (1 byte) and source select (4 bytes). For GPRs type is 0
308 // and select is 0 (GPR index is encoded in the instr encoding. For constants
309 // type is 1 and select is the original const select passed from the driver.
310 unsigned Reg = RegMO.getReg();
311 if (Reg == AMDGPU::ALU_CONST) {
313 uint32_t Sel = SelMO.getImm();
317 Emit((uint32_t)0, OS);
320 if (Reg == AMDGPU::ALU_LITERAL_X) {
321 unsigned ImmOpIndex = MI.getNumOperands() - 1;
322 MCOperand ImmOp = MI.getOperand(ImmOpIndex);
323 if (ImmOp.isFPImm()) {
324 InlineConstant.f = ImmOp.getFPImm();
326 assert(ImmOp.isImm());
327 InlineConstant.i = ImmOp.getImm();
331 // Emit the literal value, if applicable (4 bytes).
332 Emit(InlineConstant.i, OS);
335 void R600MCCodeEmitter::EmitTexInstr(const MCInst &MI,
336 SmallVectorImpl<MCFixup> &Fixups,
337 raw_ostream &OS) const {
339 unsigned Opcode = MI.getOpcode();
340 bool hasOffsets = (Opcode == AMDGPU::TEX_LD);
341 unsigned OpOffset = hasOffsets ? 3 : 0;
342 int64_t Resource = MI.getOperand(OpOffset + 2).getImm();
343 int64_t Sampler = MI.getOperand(OpOffset + 3).getImm();
344 int64_t TextureType = MI.getOperand(OpOffset + 4).getImm();
345 unsigned srcSelect[4] = {0, 1, 2, 3};
347 // Emit instruction type
351 EmitByte(getBinaryCodeForInstr(MI, Fixups), OS);
354 EmitByte(Resource, OS);
356 // Emit source register
357 EmitByte(getHWReg(MI.getOperand(1).getReg()), OS);
359 // XXX: Emit src isRelativeAddress
362 // Emit destination register
363 EmitByte(getHWReg(MI.getOperand(0).getReg()), OS);
365 // XXX: Emit dst isRealtiveAddress
368 // XXX: Emit dst select
369 EmitByte(0, OS); // X
370 EmitByte(1, OS); // Y
371 EmitByte(2, OS); // Z
372 EmitByte(3, OS); // W
374 // XXX: Emit lod bias
377 // XXX: Emit coord types
378 unsigned coordType[4] = {1, 1, 1, 1};
380 if (TextureType == TEXTURE_RECT
381 || TextureType == TEXTURE_SHADOWRECT) {
382 coordType[ELEMENT_X] = 0;
383 coordType[ELEMENT_Y] = 0;
386 if (TextureType == TEXTURE_1D_ARRAY
387 || TextureType == TEXTURE_SHADOW1D_ARRAY) {
388 if (Opcode == AMDGPU::TEX_SAMPLE_C_L || Opcode == AMDGPU::TEX_SAMPLE_C_LB) {
389 coordType[ELEMENT_Y] = 0;
391 coordType[ELEMENT_Z] = 0;
392 srcSelect[ELEMENT_Z] = ELEMENT_Y;
394 } else if (TextureType == TEXTURE_2D_ARRAY
395 || TextureType == TEXTURE_SHADOW2D_ARRAY) {
396 coordType[ELEMENT_Z] = 0;
399 for (unsigned i = 0; i < 4; i++) {
400 EmitByte(coordType[i], OS);
405 for (unsigned i = 2; i < 5; i++)
406 EmitByte(MI.getOperand(i).getImm()<<1, OS);
408 EmitNullBytes(3, OS);
411 EmitByte(Sampler, OS);
413 // XXX:Emit source select
414 if ((TextureType == TEXTURE_SHADOW1D
415 || TextureType == TEXTURE_SHADOW2D
416 || TextureType == TEXTURE_SHADOWRECT
417 || TextureType == TEXTURE_SHADOW1D_ARRAY)
418 && Opcode != AMDGPU::TEX_SAMPLE_C_L
419 && Opcode != AMDGPU::TEX_SAMPLE_C_LB) {
420 srcSelect[ELEMENT_W] = ELEMENT_Z;
423 for (unsigned i = 0; i < 4; i++) {
424 EmitByte(srcSelect[i], OS);
428 void R600MCCodeEmitter::EmitFCInstr(const MCInst &MI, raw_ostream &OS) const {
430 // Emit instruction type
431 EmitByte(INSTR_FC, OS);
434 unsigned NumOperands = MI.getNumOperands();
435 if (NumOperands > 0) {
436 assert(NumOperands == 1);
439 EmitNullBytes(SRC_BYTE_COUNT, OS);
442 // Emit FC Instruction
444 switch (MI.getOpcode()) {
445 case AMDGPU::PREDICATED_BREAK:
446 instr = FC_BREAK_PREDICATE;
448 case AMDGPU::CONTINUE:
451 case AMDGPU::IF_PREDICATE_SET:
452 instr = FC_IF_PREDICATE;
460 case AMDGPU::ENDLOOP:
463 case AMDGPU::WHILELOOP:
473 void R600MCCodeEmitter::EmitNullBytes(unsigned int ByteCount,
474 raw_ostream &OS) const {
476 for (unsigned int i = 0; i < ByteCount; i++) {
481 void R600MCCodeEmitter::EmitByte(unsigned int Byte, raw_ostream &OS) const {
482 OS.write((uint8_t) Byte & 0xff);
485 void R600MCCodeEmitter::EmitTwoBytes(unsigned int Bytes,
486 raw_ostream &OS) const {
487 OS.write((uint8_t) (Bytes & 0xff));
488 OS.write((uint8_t) ((Bytes >> 8) & 0xff));
491 void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const {
492 for (unsigned i = 0; i < 4; i++) {
493 OS.write((uint8_t) ((Value >> (8 * i)) & 0xff));
497 void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const {
498 for (unsigned i = 0; i < 8; i++) {
499 EmitByte((Value >> (8 * i)) & 0xff, OS);
503 unsigned R600MCCodeEmitter::getHWRegChan(unsigned reg) const {
504 return MRI.getEncodingValue(reg) >> HW_CHAN_SHIFT;
507 unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
508 return MRI.getEncodingValue(RegNo) & HW_REG_MASK;
511 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
513 SmallVectorImpl<MCFixup> &Fixup) const {
515 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) {
516 return MRI.getEncodingValue(MO.getReg());
518 return getHWReg(MO.getReg());
520 } else if (MO.isImm()) {
528 //===----------------------------------------------------------------------===//
529 // Encoding helper functions
530 //===----------------------------------------------------------------------===//
532 bool R600MCCodeEmitter::isFCOp(unsigned opcode) const {
534 default: return false;
535 case AMDGPU::PREDICATED_BREAK:
536 case AMDGPU::CONTINUE:
537 case AMDGPU::IF_PREDICATE_SET:
540 case AMDGPU::ENDLOOP:
541 case AMDGPU::WHILELOOP:
546 bool R600MCCodeEmitter::isTexOp(unsigned opcode) const {
548 default: return false;
550 case AMDGPU::TEX_GET_TEXTURE_RESINFO:
551 case AMDGPU::TEX_SAMPLE:
552 case AMDGPU::TEX_SAMPLE_C:
553 case AMDGPU::TEX_SAMPLE_L:
554 case AMDGPU::TEX_SAMPLE_C_L:
555 case AMDGPU::TEX_SAMPLE_LB:
556 case AMDGPU::TEX_SAMPLE_C_LB:
557 case AMDGPU::TEX_SAMPLE_G:
558 case AMDGPU::TEX_SAMPLE_C_G:
559 case AMDGPU::TEX_GET_GRADIENTS_H:
560 case AMDGPU::TEX_GET_GRADIENTS_V:
561 case AMDGPU::TEX_SET_GRADIENTS_H:
562 case AMDGPU::TEX_SET_GRADIENTS_V:
567 bool R600MCCodeEmitter::isFlagSet(const MCInst &MI, unsigned Operand,
568 unsigned Flag) const {
569 const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode());
570 unsigned FlagIndex = GET_FLAG_OPERAND_IDX(MCDesc.TSFlags);
571 if (FlagIndex == 0) {
574 assert(MI.getOperand(FlagIndex).isImm());
575 return !!((MI.getOperand(FlagIndex).getImm() >>
576 (NUM_MO_FLAGS * Operand)) & Flag);
579 #include "AMDGPUGenMCCodeEmitter.inc"