1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file provides AMDGPU specific target descriptions.
13 //===----------------------------------------------------------------------===//
15 #include "AMDGPUMCTargetDesc.h"
16 #include "AMDGPUMCAsmInfo.h"
17 #include "InstPrinter/AMDGPUInstPrinter.h"
18 #include "SIDefines.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MachineLocation.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
31 #define GET_INSTRINFO_MC_DESC
32 #include "AMDGPUGenInstrInfo.inc"
34 #define GET_SUBTARGETINFO_MC_DESC
35 #include "AMDGPUGenSubtargetInfo.inc"
37 #define GET_REGINFO_MC_DESC
38 #include "AMDGPUGenRegisterInfo.inc"
40 static MCInstrInfo *createAMDGPUMCInstrInfo() {
41 MCInstrInfo *X = new MCInstrInfo();
42 InitAMDGPUMCInstrInfo(X);
46 static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) {
47 MCRegisterInfo *X = new MCRegisterInfo();
48 InitAMDGPUMCRegisterInfo(X, 0);
52 static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU,
54 MCSubtargetInfo * X = new MCSubtargetInfo();
55 InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
59 static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM,
61 CodeGenOpt::Level OL) {
62 MCCodeGenInfo *X = new MCCodeGenInfo();
63 X->InitMCCodeGenInfo(RM, CM, OL);
67 static MCInstPrinter *createAMDGPUMCInstPrinter(const Target &T,
68 unsigned SyntaxVariant,
70 const MCInstrInfo &MII,
71 const MCRegisterInfo &MRI,
72 const MCSubtargetInfo &STI) {
73 return new AMDGPUInstPrinter(MAI, MII, MRI);
76 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Ctx,
77 MCAsmBackend &MAB, raw_ostream &OS,
78 MCCodeEmitter *Emitter,
79 const MCSubtargetInfo &STI, bool RelaxAll) {
80 return createELFStreamer(Ctx, MAB, OS, Emitter, false);
83 extern "C" void LLVMInitializeR600TargetMC() {
85 RegisterMCAsmInfo<AMDGPUMCAsmInfo> Y(TheAMDGPUTarget);
86 RegisterMCAsmInfo<AMDGPUMCAsmInfo> Z(TheGCNTarget);
88 TargetRegistry::RegisterMCCodeGenInfo(TheAMDGPUTarget, createAMDGPUMCCodeGenInfo);
89 TargetRegistry::RegisterMCCodeGenInfo(TheGCNTarget, createAMDGPUMCCodeGenInfo);
91 TargetRegistry::RegisterMCInstrInfo(TheAMDGPUTarget, createAMDGPUMCInstrInfo);
92 TargetRegistry::RegisterMCInstrInfo(TheGCNTarget, createAMDGPUMCInstrInfo);
94 TargetRegistry::RegisterMCRegInfo(TheAMDGPUTarget, createAMDGPUMCRegisterInfo);
95 TargetRegistry::RegisterMCRegInfo(TheGCNTarget, createAMDGPUMCRegisterInfo);
97 TargetRegistry::RegisterMCSubtargetInfo(TheAMDGPUTarget, createAMDGPUMCSubtargetInfo);
98 TargetRegistry::RegisterMCSubtargetInfo(TheGCNTarget, createAMDGPUMCSubtargetInfo);
100 TargetRegistry::RegisterMCInstPrinter(TheAMDGPUTarget, createAMDGPUMCInstPrinter);
101 TargetRegistry::RegisterMCInstPrinter(TheGCNTarget, createAMDGPUMCInstPrinter);
103 TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget, createR600MCCodeEmitter);
104 TargetRegistry::RegisterMCCodeEmitter(TheGCNTarget, createSIMCCodeEmitter);
106 TargetRegistry::RegisterMCAsmBackend(TheAMDGPUTarget, createAMDGPUAsmBackend);
107 TargetRegistry::RegisterMCAsmBackend(TheGCNTarget, createAMDGPUAsmBackend);
109 TargetRegistry::RegisterMCObjectStreamer(TheAMDGPUTarget, createMCStreamer);
110 TargetRegistry::RegisterMCObjectStreamer(TheGCNTarget, createMCStreamer);