1 //===-- AMDGPUAsmBackend.cpp - AMDGPU Assembler Backend -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12 #include "MCTargetDesc/AMDGPUFixupKinds.h"
13 #include "llvm/ADT/StringRef.h"
14 #include "llvm/MC/MCAsmBackend.h"
15 #include "llvm/MC/MCAssembler.h"
16 #include "llvm/MC/MCFixupKindInfo.h"
17 #include "llvm/MC/MCObjectWriter.h"
18 #include "llvm/MC/MCValue.h"
19 #include "llvm/Support/TargetRegistry.h"
25 class AMDGPUMCObjectWriter : public MCObjectWriter {
27 AMDGPUMCObjectWriter(raw_ostream &OS) : MCObjectWriter(OS, true) { }
28 void ExecutePostLayoutBinding(MCAssembler &Asm,
29 const MCAsmLayout &Layout) override {
30 //XXX: Implement if necessary.
32 void RecordRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout,
33 const MCFragment *Fragment, const MCFixup &Fixup,
34 MCValue Target, bool &IsPCRel,
35 uint64_t &FixedValue) override {
36 assert(!"Not implemented");
39 void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout) override;
43 class AMDGPUAsmBackend : public MCAsmBackend {
45 AMDGPUAsmBackend(const Target &T)
48 unsigned getNumFixupKinds() const override { return AMDGPU::NumTargetFixupKinds; };
49 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
50 uint64_t Value, bool IsPCRel) const override;
51 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
52 const MCRelaxableFragment *DF,
53 const MCAsmLayout &Layout) const override {
56 void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
57 assert(!"Not implemented");
59 bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
60 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
64 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
67 } //End anonymous namespace
69 void AMDGPUMCObjectWriter::WriteObject(MCAssembler &Asm,
70 const MCAsmLayout &Layout) {
71 for (MCAssembler::iterator I = Asm.begin(), E = Asm.end(); I != E; ++I) {
72 Asm.writeSectionData(I, Layout);
76 void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
77 unsigned DataSize, uint64_t Value,
80 switch ((unsigned)Fixup.getKind()) {
81 default: llvm_unreachable("Unknown fixup kind");
82 case AMDGPU::fixup_si_sopp_br: {
83 uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset());
84 *Dst = (Value - 4) / 4;
88 case AMDGPU::fixup_si_rodata: {
89 uint32_t *Dst = (uint32_t*)(Data + Fixup.getOffset());
94 case AMDGPU::fixup_si_end_of_text: {
95 uint32_t *Dst = (uint32_t*)(Data + Fixup.getOffset());
96 // The value points to the last instruction in the text section, so we
97 // need to add 4 bytes to get to the start of the constants.
104 const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
105 MCFixupKind Kind) const {
106 const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = {
107 // name offset bits flags
108 { "fixup_si_sopp_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
109 { "fixup_si_rodata", 0, 32, 0 },
110 { "fixup_si_end_of_text", 0, 32, MCFixupKindInfo::FKF_IsPCRel }
113 if (Kind < FirstTargetFixupKind)
114 return MCAsmBackend::getFixupKindInfo(Kind);
116 return Infos[Kind - FirstTargetFixupKind];
119 //===----------------------------------------------------------------------===//
120 // ELFAMDGPUAsmBackend class
121 //===----------------------------------------------------------------------===//
125 class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
127 ELFAMDGPUAsmBackend(const Target &T) : AMDGPUAsmBackend(T) { }
129 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
130 return createAMDGPUELFObjectWriter(OS);
134 } // end anonymous namespace
136 MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
137 const MCRegisterInfo &MRI,
140 return new ELFAMDGPUAsmBackend(T);