1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "AMDGPUInstPrinter.h"
12 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
13 #include "SIDefines.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCInstrInfo.h"
17 #include "llvm/MC/MCRegisterInfo.h"
18 #include "llvm/Support/MathExtras.h"
22 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
23 StringRef Annot, const MCSubtargetInfo &STI) {
25 printInstruction(MI, OS);
27 printAnnotation(OS, Annot);
30 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
32 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
35 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
37 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff);
40 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
42 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
45 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
47 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
50 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
52 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
55 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
57 if (MI->getOperand(OpNo).getImm())
61 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
63 if (MI->getOperand(OpNo).getImm())
67 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
69 if (MI->getOperand(OpNo).getImm())
73 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
75 if (MI->getOperand(OpNo).getImm()) {
77 printU16ImmDecOperand(MI, OpNo, O);
81 void AMDGPUInstPrinter::printDSOffset(const MCInst *MI, unsigned OpNo,
83 uint16_t Imm = MI->getOperand(OpNo).getImm();
86 printU16ImmDecOperand(MI, OpNo, O);
90 void AMDGPUInstPrinter::printDSOffset0(const MCInst *MI, unsigned OpNo,
92 if (MI->getOperand(OpNo).getImm()) {
94 printU8ImmDecOperand(MI, OpNo, O);
98 void AMDGPUInstPrinter::printDSOffset1(const MCInst *MI, unsigned OpNo,
100 if (MI->getOperand(OpNo).getImm()) {
102 printU8ImmDecOperand(MI, OpNo, O);
106 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
108 if (MI->getOperand(OpNo).getImm())
112 void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
114 if (MI->getOperand(OpNo).getImm())
118 void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
120 if (MI->getOperand(OpNo).getImm())
124 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
126 if (MI->getOperand(OpNo).getImm())
130 void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) {
144 case AMDGPU::FLAT_SCR:
153 case AMDGPU::EXEC_LO:
156 case AMDGPU::EXEC_HI:
159 case AMDGPU::FLAT_SCR_LO:
160 O << "flat_scratch_lo";
162 case AMDGPU::FLAT_SCR_HI:
163 O << "flat_scratch_hi";
172 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) {
175 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) {
178 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) {
181 } else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) {
184 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) {
187 } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) {
190 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) {
193 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) {
196 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) {
199 } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(reg)) {
202 } else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(reg)) {
206 O << getRegisterName(reg);
210 // The low 8 bits of the encoding value is the register index, for both VGPRs
212 unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1);
218 O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
221 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
223 if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3)
228 printOperand(MI, OpNo, O);
231 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, raw_ostream &O) {
232 int32_t SImm = static_cast<int32_t>(Imm);
233 if (SImm >= -16 && SImm <= 64) {
238 if (Imm == FloatToBits(0.0f))
240 else if (Imm == FloatToBits(1.0f))
242 else if (Imm == FloatToBits(-1.0f))
244 else if (Imm == FloatToBits(0.5f))
246 else if (Imm == FloatToBits(-0.5f))
248 else if (Imm == FloatToBits(2.0f))
250 else if (Imm == FloatToBits(-2.0f))
252 else if (Imm == FloatToBits(4.0f))
254 else if (Imm == FloatToBits(-4.0f))
257 O << formatHex(static_cast<uint64_t>(Imm));
260 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm, raw_ostream &O) {
261 int64_t SImm = static_cast<int64_t>(Imm);
262 if (SImm >= -16 && SImm <= 64) {
267 if (Imm == DoubleToBits(0.0))
269 else if (Imm == DoubleToBits(1.0))
271 else if (Imm == DoubleToBits(-1.0))
273 else if (Imm == DoubleToBits(0.5))
275 else if (Imm == DoubleToBits(-0.5))
277 else if (Imm == DoubleToBits(2.0))
279 else if (Imm == DoubleToBits(-2.0))
281 else if (Imm == DoubleToBits(4.0))
283 else if (Imm == DoubleToBits(-4.0))
286 llvm_unreachable("64-bit literal constants not supported");
289 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
292 const MCOperand &Op = MI->getOperand(OpNo);
294 switch (Op.getReg()) {
295 // This is the default predicate state, so we don't need to print it.
296 case AMDGPU::PRED_SEL_OFF:
300 printRegOperand(Op.getReg(), O);
303 } else if (Op.isImm()) {
304 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
305 int RCID = Desc.OpInfo[OpNo].RegClass;
307 const MCRegisterClass &ImmRC = MRI.getRegClass(RCID);
308 if (ImmRC.getSize() == 4)
309 printImmediate32(Op.getImm(), O);
310 else if (ImmRC.getSize() == 8)
311 printImmediate64(Op.getImm(), O);
313 llvm_unreachable("Invalid register class size");
314 } else if (Desc.OpInfo[OpNo].OperandType == MCOI::OPERAND_IMMEDIATE) {
315 printImmediate32(Op.getImm(), O);
317 // We hit this for the immediate instruction bits that don't yet have a
319 // TODO: Eventually this should be unnecessary.
320 O << formatDec(Op.getImm());
322 } else if (Op.isFPImm()) {
323 // We special case 0.0 because otherwise it will be printed as an integer.
324 if (Op.getFPImm() == 0.0)
327 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
328 const MCRegisterClass &ImmRC = MRI.getRegClass(Desc.OpInfo[OpNo].RegClass);
330 if (ImmRC.getSize() == 4)
331 printImmediate32(FloatToBits(Op.getFPImm()), O);
332 else if (ImmRC.getSize() == 8)
333 printImmediate64(DoubleToBits(Op.getFPImm()), O);
335 llvm_unreachable("Invalid register class size");
337 } else if (Op.isExpr()) {
338 const MCExpr *Exp = Op.getExpr();
341 llvm_unreachable("unknown operand type in printOperand");
345 void AMDGPUInstPrinter::printOperandAndMods(const MCInst *MI, unsigned OpNo,
347 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
348 if (InputModifiers & SISrcMods::NEG)
350 if (InputModifiers & SISrcMods::ABS)
352 printOperand(MI, OpNo + 1, O);
353 if (InputModifiers & SISrcMods::ABS)
357 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
359 unsigned Imm = MI->getOperand(OpNum).getImm();
363 } else if (Imm == 1) {
365 } else if (Imm == 0) {
368 llvm_unreachable("Invalid interpolation parameter slot");
372 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
374 printOperand(MI, OpNo, O);
376 printOperand(MI, OpNo + 1, O);
379 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
380 raw_ostream &O, StringRef Asm,
382 const MCOperand &Op = MI->getOperand(OpNo);
384 if (Op.getImm() == 1) {
391 void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
393 printIfSet(MI, OpNo, O, "|");
396 void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
398 printIfSet(MI, OpNo, O, "_SAT");
401 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
403 if (MI->getOperand(OpNo).getImm())
407 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
409 int Imm = MI->getOperand(OpNo).getImm();
410 if (Imm == SIOutMods::MUL2)
412 else if (Imm == SIOutMods::MUL4)
414 else if (Imm == SIOutMods::DIV2)
418 void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
420 int32_t Imm = MI->getOperand(OpNo).getImm();
421 O << Imm << '(' << BitsToFloat(Imm) << ')';
424 void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
426 printIfSet(MI, OpNo, O.indent(25 - O.GetNumBytesInBuffer()), "*", " ");
429 void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
431 printIfSet(MI, OpNo, O, "-");
434 void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
436 switch (MI->getOperand(OpNo).getImm()) {
450 void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo,
452 printIfSet(MI, OpNo, O, "+");
455 void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
457 printIfSet(MI, OpNo, O, "ExecMask,");
460 void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
462 printIfSet(MI, OpNo, O, "Pred,");
465 void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
467 const MCOperand &Op = MI->getOperand(OpNo);
468 if (Op.getImm() == 0) {
473 void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
475 const char * chans = "XYZW";
476 int sel = MI->getOperand(OpNo).getImm();
485 O << cb << '[' << sel << ']';
486 } else if (sel >= 448) {
489 } else if (sel >= 0){
494 O << '.' << chans[chan];
497 void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
499 int BankSwizzle = MI->getOperand(OpNo).getImm();
500 switch (BankSwizzle) {
502 O << "BS:VEC_021/SCL_122";
505 O << "BS:VEC_120/SCL_212";
508 O << "BS:VEC_102/SCL_221";
522 void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
524 unsigned Sel = MI->getOperand(OpNo).getImm();
552 void AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo,
554 unsigned CT = MI->getOperand(OpNo).getImm();
567 void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
569 int KCacheMode = MI->getOperand(OpNo).getImm();
570 if (KCacheMode > 0) {
571 int KCacheBank = MI->getOperand(OpNo - 2).getImm();
572 O << "CB" << KCacheBank << ':';
573 int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
574 int LineSize = (KCacheMode == 1) ? 16 : 32;
575 O << KCacheAddr * 16 << '-' << KCacheAddr * 16 + LineSize;
579 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
581 unsigned SImm16 = MI->getOperand(OpNo).getImm();
582 unsigned Msg = SImm16 & 0xF;
583 if (Msg == 2 || Msg == 3) {
584 unsigned Op = (SImm16 >> 4) & 0xF;
592 unsigned Stream = (SImm16 >> 8) & 0x3;
599 O << " stream " << Stream;
607 O << "unknown(" << Msg << ") ";
610 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
612 // Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs
613 // SIInsertWaits.cpp bits usage does not match ISA docs description but it
614 // works so it might be a misprint in docs.
615 unsigned SImm16 = MI->getOperand(OpNo).getImm();
616 unsigned Vmcnt = SImm16 & 0xF;
617 unsigned Expcnt = (SImm16 >> 4) & 0xF;
618 unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
620 bool NeedSpace = false;
623 O << "vmcnt(" << Vmcnt << ')';
630 O << "expcnt(" << Expcnt << ')';
634 if (Lgkmcnt != 0x7) {
637 O << "lgkmcnt(" << Lgkmcnt << ')';
641 #include "AMDGPUGenAsmWriter.inc"