1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "AMDGPUInstPrinter.h"
12 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCRegisterInfo.h"
16 #include "llvm/Support/MathExtras.h"
20 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
23 printInstruction(MI, OS);
25 printAnnotation(OS, Annot);
28 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
30 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
33 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
35 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff);
38 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
40 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
43 void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) {
64 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) {
67 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) {
70 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) {
73 } else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) {
76 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) {
79 } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) {
82 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) {
85 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) {
88 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) {
91 } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(reg)) {
94 } else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(reg)) {
98 O << getRegisterName(reg);
102 // The low 8 bits of the encoding value is the register index, for both VGPRs
104 unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1);
110 O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
113 void AMDGPUInstPrinter::printImmediate(uint32_t Imm, raw_ostream &O) {
114 int32_t SImm = static_cast<int32_t>(Imm);
115 if (SImm >= -16 && SImm <= 64) {
120 if (Imm == FloatToBits(1.0f) ||
121 Imm == FloatToBits(-1.0f) ||
122 Imm == FloatToBits(0.5f) ||
123 Imm == FloatToBits(-0.5f) ||
124 Imm == FloatToBits(2.0f) ||
125 Imm == FloatToBits(-2.0f) ||
126 Imm == FloatToBits(4.0f) ||
127 Imm == FloatToBits(-4.0f)) {
128 O << BitsToFloat(Imm);
132 O << formatHex(static_cast<uint64_t>(Imm));
135 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
138 const MCOperand &Op = MI->getOperand(OpNo);
140 switch (Op.getReg()) {
141 // This is the default predicate state, so we don't need to print it.
142 case AMDGPU::PRED_SEL_OFF:
146 printRegOperand(Op.getReg(), O);
149 } else if (Op.isImm()) {
150 printImmediate(Op.getImm(), O);
151 } else if (Op.isFPImm()) {
153 } else if (Op.isExpr()) {
154 const MCExpr *Exp = Op.getExpr();
157 assert(!"unknown operand type in printOperand");
161 void AMDGPUInstPrinter::printOperandAndMods(const MCInst *MI, unsigned OpNo,
163 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
164 if (InputModifiers & 0x1)
166 if (InputModifiers & 0x2)
168 printOperand(MI, OpNo + 1, O);
169 if (InputModifiers & 0x2)
173 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
175 unsigned Imm = MI->getOperand(OpNum).getImm();
179 } else if (Imm == 1) {
181 } else if (Imm == 0) {
184 assert(!"Invalid interpolation parameter slot");
188 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
190 printOperand(MI, OpNo, O);
192 printOperand(MI, OpNo + 1, O);
195 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
196 raw_ostream &O, StringRef Asm,
198 const MCOperand &Op = MI->getOperand(OpNo);
200 if (Op.getImm() == 1) {
207 void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
209 printIfSet(MI, OpNo, O, "|");
212 void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
214 printIfSet(MI, OpNo, O, "_SAT");
217 void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
219 int32_t Imm = MI->getOperand(OpNo).getImm();
220 O << Imm << '(' << BitsToFloat(Imm) << ')';
223 void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
225 printIfSet(MI, OpNo, O.indent(25 - O.GetNumBytesInBuffer()), "*", " ");
228 void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
230 printIfSet(MI, OpNo, O, "-");
233 void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
235 switch (MI->getOperand(OpNo).getImm()) {
249 void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo,
251 printIfSet(MI, OpNo, O, "+");
254 void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
256 printIfSet(MI, OpNo, O, "ExecMask,");
259 void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
261 printIfSet(MI, OpNo, O, "Pred,");
264 void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
266 const MCOperand &Op = MI->getOperand(OpNo);
267 if (Op.getImm() == 0) {
272 void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
274 const char * chans = "XYZW";
275 int sel = MI->getOperand(OpNo).getImm();
284 O << cb << "[" << sel << "]";
285 } else if (sel >= 448) {
288 } else if (sel >= 0){
293 O << "." << chans[chan];
296 void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
298 int BankSwizzle = MI->getOperand(OpNo).getImm();
299 switch (BankSwizzle) {
301 O << "BS:VEC_021/SCL_122";
304 O << "BS:VEC_120/SCL_212";
307 O << "BS:VEC_102/SCL_221";
321 void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
323 unsigned Sel = MI->getOperand(OpNo).getImm();
351 void AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo,
353 unsigned CT = MI->getOperand(OpNo).getImm();
366 void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
368 int KCacheMode = MI->getOperand(OpNo).getImm();
369 if (KCacheMode > 0) {
370 int KCacheBank = MI->getOperand(OpNo - 2).getImm();
371 O << "CB" << KCacheBank <<":";
372 int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
373 int LineSize = (KCacheMode == 1)?16:32;
374 O << KCacheAddr * 16 << "-" << KCacheAddr * 16 + LineSize;
378 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
380 unsigned SImm16 = MI->getOperand(OpNo).getImm();
381 unsigned Msg = SImm16 & 0xF;
382 if (Msg == 2 || Msg == 3) {
383 unsigned Op = (SImm16 >> 4) & 0xF;
391 unsigned Stream = (SImm16 >> 8) & 0x3;
398 O << " stream " << Stream;
406 O << "unknown(" << Msg << ") ";
409 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
411 // Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs
412 // SIInsertWaits.cpp bits usage does not match ISA docs description but it
413 // works so it might be a misprint in docs.
414 unsigned SImm16 = MI->getOperand(OpNo).getImm();
415 unsigned Vmcnt = SImm16 & 0xF;
416 unsigned Expcnt = (SImm16 >> 4) & 0xF;
417 unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
419 O << "vmcnt(" << Vmcnt << ") ";
421 O << "expcnt(" << Expcnt << ") ";
423 O << "lgkmcnt(" << Lgkmcnt << ")";
426 #include "AMDGPUGenAsmWriter.inc"