1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information needed to emit code for R600 and SI GPUs.
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUTargetMachine.h"
18 #include "R600ISelLowering.h"
19 #include "R600InstrInfo.h"
20 #include "R600MachineScheduler.h"
21 #include "SIISelLowering.h"
22 #include "SIInstrInfo.h"
23 #include "llvm/Analysis/Passes.h"
24 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/IR/Verifier.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/PassManager.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_os_ostream.h"
32 #include "llvm/Transforms/IPO.h"
33 #include "llvm/Transforms/Scalar.h"
34 #include <llvm/CodeGen/Passes.h>
39 extern "C" void LLVMInitializeR600Target() {
40 // Register the target
41 RegisterTargetMachine<AMDGPUTargetMachine> X(TheAMDGPUTarget);
44 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
45 return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>());
48 static MachineSchedRegistry
49 SchedCustomRegistry("r600", "Run R600's custom scheduler",
50 createR600MachineScheduler);
52 static std::string computeDataLayout(const AMDGPUSubtarget &ST) {
53 std::string Ret = "e-p:32:32";
56 // 32-bit private, local, and region pointers. 64-bit global and constant.
57 Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64";
60 Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
61 "-v512:512-v1024:1024-v2048:2048-n32:64";
66 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
67 StringRef CPU, StringRef FS,
68 TargetOptions Options,
69 Reloc::Model RM, CodeModel::Model CM,
70 CodeGenOpt::Level OptLevel
73 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
74 Subtarget(TT, CPU, FS),
75 Layout(computeDataLayout(Subtarget)),
76 FrameLowering(TargetFrameLowering::StackGrowsUp,
77 64 * 16 // Maximum stack alignment (long16)
80 InstrItins(&Subtarget.getInstrItineraryData()) {
81 // TLInfo uses InstrInfo so it must be initialized after.
82 if (Subtarget.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
83 TLInfo.reset(new R600TargetLowering(*this));
85 TLInfo.reset(new SITargetLowering(*this));
87 setRequiresStructuredCFG(true);
91 AMDGPUTargetMachine::~AMDGPUTargetMachine() {
95 class AMDGPUPassConfig : public TargetPassConfig {
97 AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM)
98 : TargetPassConfig(TM, PM) {}
100 AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
101 return getTM<AMDGPUTargetMachine>();
105 createMachineScheduler(MachineSchedContext *C) const override {
106 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
107 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
108 return createR600MachineScheduler(C);
112 bool addPreISel() override;
113 bool addInstSelector() override;
114 bool addPreRegAlloc() override;
115 bool addPostRegAlloc() override;
116 bool addPreSched2() override;
117 bool addPreEmitPass() override;
119 } // End of anonymous namespace
121 TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
122 return new AMDGPUPassConfig(this, PM);
125 //===----------------------------------------------------------------------===//
126 // AMDGPU Analysis Pass Setup
127 //===----------------------------------------------------------------------===//
129 void AMDGPUTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
130 // Add first the target-independent BasicTTI pass, then our AMDGPU pass. This
131 // allows the AMDGPU pass to delegate to the target independent layer when
133 PM.add(createBasicTargetTransformInfoPass(this));
134 PM.add(createAMDGPUTargetTransformInfoPass(this));
138 AMDGPUPassConfig::addPreISel() {
139 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
140 addPass(createFlattenCFGPass());
141 if (ST.IsIRStructurizerEnabled())
142 addPass(createStructurizeCFGPass());
143 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
144 addPass(createSinkingPass());
145 addPass(createSITypeRewriter());
146 addPass(createSIAnnotateControlFlowPass());
148 addPass(createR600TextureIntrinsicsReplacer());
153 bool AMDGPUPassConfig::addInstSelector() {
154 addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
155 addPass(createSILowerI1CopiesPass());
159 bool AMDGPUPassConfig::addPreRegAlloc() {
160 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
162 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
163 addPass(createR600VectorRegMerger(*TM));
165 addPass(createSIFixSGPRCopiesPass(*TM));
166 // SIFixSGPRCopies can generate a lot of duplicate instructions,
167 // so we need to run MachineCSE afterwards.
168 addPass(&MachineCSEID);
173 bool AMDGPUPassConfig::addPostRegAlloc() {
174 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
176 if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
177 addPass(createSIInsertWaits(*TM));
182 bool AMDGPUPassConfig::addPreSched2() {
183 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
185 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
186 addPass(createR600EmitClauseMarkers());
187 if (ST.isIfCvtEnabled())
188 addPass(&IfConverterID);
189 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
190 addPass(createR600ClauseMergePass(*TM));
194 bool AMDGPUPassConfig::addPreEmitPass() {
195 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
196 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
197 addPass(createAMDGPUCFGStructurizerPass());
198 addPass(createR600ExpandSpecialInstrsPass(*TM));
199 addPass(&FinalizeMachineBundlesID);
200 addPass(createR600Packetizer(*TM));
201 addPass(createR600ControlFlowFinalizer(*TM));
203 addPass(createSILowerControlFlowPass(*TM));