1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information needed to emit code for R600 and SI GPUs.
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUTargetMachine.h"
18 #include "R600ISelLowering.h"
19 #include "R600InstrInfo.h"
20 #include "R600MachineScheduler.h"
21 #include "SIISelLowering.h"
22 #include "SIInstrInfo.h"
23 #include "llvm/Analysis/Passes.h"
24 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/IR/Verifier.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/PassManager.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Support/raw_os_ostream.h"
33 #include "llvm/Transforms/IPO.h"
34 #include "llvm/Transforms/Scalar.h"
35 #include <llvm/CodeGen/Passes.h>
39 extern "C" void LLVMInitializeR600Target() {
40 // Register the target
41 RegisterTargetMachine<AMDGPUTargetMachine> X(TheAMDGPUTarget);
44 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
45 return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>());
48 static MachineSchedRegistry
49 SchedCustomRegistry("r600", "Run R600's custom scheduler",
50 createR600MachineScheduler);
52 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
53 StringRef CPU, StringRef FS,
54 TargetOptions Options, Reloc::Model RM,
56 CodeGenOpt::Level OptLevel)
57 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
58 TLOF(new TargetLoweringObjectFileELF()),
59 Subtarget(TT, CPU, FS, *this), IntrinsicInfo() {
60 setRequiresStructuredCFG(true);
64 AMDGPUTargetMachine::~AMDGPUTargetMachine() {
69 class AMDGPUPassConfig : public TargetPassConfig {
71 AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM)
72 : TargetPassConfig(TM, PM) {}
74 AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
75 return getTM<AMDGPUTargetMachine>();
79 createMachineScheduler(MachineSchedContext *C) const override {
80 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
81 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
82 return createR600MachineScheduler(C);
86 void addIRPasses() override;
87 void addCodeGenPrepare() override;
88 bool addPreISel() override;
89 bool addInstSelector() override;
90 bool addPreRegAlloc() override;
91 bool addPostRegAlloc() override;
92 bool addPreSched2() override;
93 bool addPreEmitPass() override;
95 } // End of anonymous namespace
97 TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
98 return new AMDGPUPassConfig(this, PM);
101 //===----------------------------------------------------------------------===//
102 // AMDGPU Analysis Pass Setup
103 //===----------------------------------------------------------------------===//
105 void AMDGPUTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
106 // Add first the target-independent BasicTTI pass, then our AMDGPU pass. This
107 // allows the AMDGPU pass to delegate to the target independent layer when
109 PM.add(createBasicTargetTransformInfoPass(this));
110 PM.add(createAMDGPUTargetTransformInfoPass(this));
113 void AMDGPUPassConfig::addIRPasses() {
114 // Function calls are not supported, so make sure we inline everything.
115 addPass(createAMDGPUAlwaysInlinePass());
116 addPass(createAlwaysInlinerPass());
117 // We need to add the barrier noop pass, otherwise adding the function
118 // inlining pass will cause all of the PassConfigs passes to be run
119 // one function at a time, which means if we have a nodule with two
120 // functions, then we will generate code for the first function
121 // without ever running any passes on the second.
122 addPass(createBarrierNoopPass());
123 TargetPassConfig::addIRPasses();
126 void AMDGPUPassConfig::addCodeGenPrepare() {
127 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
128 if (ST.isPromoteAllocaEnabled()) {
129 addPass(createAMDGPUPromoteAlloca(ST));
130 addPass(createSROAPass());
133 TargetPassConfig::addCodeGenPrepare();
137 AMDGPUPassConfig::addPreISel() {
138 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
139 addPass(createFlattenCFGPass());
140 if (ST.IsIRStructurizerEnabled())
141 addPass(createStructurizeCFGPass());
142 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
143 addPass(createSinkingPass());
144 addPass(createSITypeRewriter());
145 addPass(createSIAnnotateControlFlowPass());
147 addPass(createR600TextureIntrinsicsReplacer());
152 bool AMDGPUPassConfig::addInstSelector() {
153 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
155 addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
157 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
158 addPass(createSILowerI1CopiesPass());
159 addPass(createSIFixSGPRCopiesPass(*TM));
160 addPass(createSIFoldOperandsPass());
166 bool AMDGPUPassConfig::addPreRegAlloc() {
167 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
169 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
170 addPass(createR600VectorRegMerger(*TM));
172 if (getOptLevel() > CodeGenOpt::None && ST.loadStoreOptEnabled()) {
173 // Don't do this with no optimizations since it throws away debug info by
174 // merging nonadjacent loads.
176 // This should be run after scheduling, but before register allocation. It
177 // also need extra copies to the address operand to be eliminated.
178 initializeSILoadStoreOptimizerPass(*PassRegistry::getPassRegistry());
179 insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID);
182 addPass(createSIShrinkInstructionsPass());
183 addPass(createSIFixSGPRLiveRangesPass());
188 bool AMDGPUPassConfig::addPostRegAlloc() {
189 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
191 if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
192 addPass(createSIShrinkInstructionsPass());
197 bool AMDGPUPassConfig::addPreSched2() {
198 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
200 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
201 addPass(createR600EmitClauseMarkers());
202 if (ST.isIfCvtEnabled())
203 addPass(&IfConverterID);
204 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
205 addPass(createR600ClauseMergePass(*TM));
206 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
207 addPass(createSIInsertWaits(*TM));
212 bool AMDGPUPassConfig::addPreEmitPass() {
213 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
214 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
215 addPass(createAMDGPUCFGStructurizerPass());
216 addPass(createR600ExpandSpecialInstrsPass(*TM));
217 addPass(&FinalizeMachineBundlesID);
218 addPass(createR600Packetizer(*TM));
219 addPass(createR600ControlFlowFinalizer(*TM));
221 addPass(createSILowerControlFlowPass(*TM));