1 //===-- AMDGPUSubtarget.cpp - AMDGPU Subtarget Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Implements the AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #include "AMDGPUSubtarget.h"
16 #include "R600ISelLowering.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineScheduler.h"
19 #include "SIISelLowering.h"
20 #include "SIInstrInfo.h"
21 #include "SIMachineFunctionInfo.h"
22 #include "llvm/ADT/SmallString.h"
26 #define DEBUG_TYPE "amdgpu-subtarget"
28 #define GET_SUBTARGETINFO_ENUM
29 #define GET_SUBTARGETINFO_TARGET_DESC
30 #define GET_SUBTARGETINFO_CTOR
31 #include "AMDGPUGenSubtargetInfo.inc"
34 AMDGPUSubtarget::initializeSubtargetDependencies(StringRef TT, StringRef GPU, StringRef FS) {
35 // Determine default and user-specified characteristics
36 // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
37 // enabled, but some instructions do not respect them and they run at the
38 // double precision rate, so don't enable by default.
40 // We want to be able to turn these off, but making this a subtarget feature
41 // for SI has the unhelpful behavior that it unsets everything else if you
44 SmallString<256> FullFS("+promote-alloca,+fp64-denormals,");
47 if (GPU == "" && Triple(TT).getArch() == Triple::amdgcn)
50 ParseSubtargetFeatures(GPU, FullFS);
52 // FIXME: I don't think think Evergreen has any useful support for
53 // denormals, but should be checked. Should we issue a warning somewhere
54 // if someone tries to enable these?
55 if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
56 FP32Denormals = false;
57 FP64Denormals = false;
62 AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS,
64 : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false),
65 DumpCode(false), R600ALUInst(false), HasVertexCache(false),
66 TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
67 FP64Denormals(false), FP32Denormals(false), CaymanISA(false),
68 FlatAddressSpace(false), EnableIRStructurizer(true),
69 EnablePromoteAlloca(false), EnableIfCvt(true),
70 EnableLoadStoreOpt(false), WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
71 EnableVGPRSpilling(false),
72 FrameLowering(TargetFrameLowering::StackGrowsUp,
73 64 * 16, // Maximum stack alignment (long16)
75 InstrItins(getInstrItineraryForCPU(GPU)),
78 initializeSubtargetDependencies(TT, GPU, FS);
80 if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
81 InstrInfo.reset(new R600InstrInfo(*this));
82 TLInfo.reset(new R600TargetLowering(TM));
84 InstrInfo.reset(new SIInstrInfo(*this));
85 TLInfo.reset(new SITargetLowering(TM));
89 unsigned AMDGPUSubtarget::getStackEntrySize() const {
90 assert(getGeneration() <= NORTHERN_ISLANDS);
91 switch(getWavefrontSize()) {
95 return hasCaymanISA() ? 4 : 8;
99 llvm_unreachable("Illegal wavefront size.");
103 unsigned AMDGPUSubtarget::getAmdKernelCodeChipID() const {
104 switch(getGeneration()) {
105 default: llvm_unreachable("ChipID unknown");
106 case SEA_ISLANDS: return 12;
110 bool AMDGPUSubtarget::isVGPRSpillingEnabled(
111 const SIMachineFunctionInfo *MFI) const {
112 return MFI->getShaderType() == ShaderType::COMPUTE || EnableVGPRSpilling;