1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction defs that are common to all hw codegen
13 //===----------------------------------------------------------------------===//
15 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
16 field bit isRegisterLoad = 0;
17 field bit isRegisterStore = 0;
19 let Namespace = "AMDGPU";
20 let OutOperandList = outs;
21 let InOperandList = ins;
23 let Pattern = pattern;
24 let Itinerary = NullALU;
26 let TSFlags{63} = isRegisterLoad;
27 let TSFlags{62} = isRegisterStore;
30 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
31 : AMDGPUInst<outs, ins, asm, pattern> {
33 field bits<32> Inst = 0xffffffff;
37 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
38 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
40 def u32imm : Operand<i32> {
41 let PrintMethod = "printU32ImmOperand";
44 def u16imm : Operand<i16> {
45 let PrintMethod = "printU16ImmOperand";
48 def u8imm : Operand<i8> {
49 let PrintMethod = "printU8ImmOperand";
52 //===----------------------------------------------------------------------===//
53 // PatLeafs for floating-point comparisons
54 //===----------------------------------------------------------------------===//
56 def COND_OEQ : PatLeaf <
58 [{return N->get() == ISD::SETOEQ || N->get() == ISD::SETEQ;}]
61 def COND_OGT : PatLeaf <
63 [{return N->get() == ISD::SETOGT || N->get() == ISD::SETGT;}]
66 def COND_OGE : PatLeaf <
68 [{return N->get() == ISD::SETOGE || N->get() == ISD::SETGE;}]
71 def COND_OLT : PatLeaf <
73 [{return N->get() == ISD::SETOLT || N->get() == ISD::SETLT;}]
76 def COND_OLE : PatLeaf <
78 [{return N->get() == ISD::SETOLE || N->get() == ISD::SETLE;}]
81 def COND_UNE : PatLeaf <
83 [{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
86 def COND_O : PatLeaf <(cond), [{return N->get() == ISD::SETO;}]>;
87 def COND_UO : PatLeaf <(cond), [{return N->get() == ISD::SETUO;}]>;
89 //===----------------------------------------------------------------------===//
90 // PatLeafs for unsigned comparisons
91 //===----------------------------------------------------------------------===//
93 def COND_UGT : PatLeaf <(cond), [{return N->get() == ISD::SETUGT;}]>;
94 def COND_UGE : PatLeaf <(cond), [{return N->get() == ISD::SETUGE;}]>;
95 def COND_ULT : PatLeaf <(cond), [{return N->get() == ISD::SETULT;}]>;
96 def COND_ULE : PatLeaf <(cond), [{return N->get() == ISD::SETULE;}]>;
98 //===----------------------------------------------------------------------===//
99 // PatLeafs for signed comparisons
100 //===----------------------------------------------------------------------===//
102 def COND_SGT : PatLeaf <(cond), [{return N->get() == ISD::SETGT;}]>;
103 def COND_SGE : PatLeaf <(cond), [{return N->get() == ISD::SETGE;}]>;
104 def COND_SLT : PatLeaf <(cond), [{return N->get() == ISD::SETLT;}]>;
105 def COND_SLE : PatLeaf <(cond), [{return N->get() == ISD::SETLE;}]>;
107 //===----------------------------------------------------------------------===//
108 // PatLeafs for integer equality
109 //===----------------------------------------------------------------------===//
111 def COND_EQ : PatLeaf <
113 [{return N->get() == ISD::SETEQ || N->get() == ISD::SETUEQ;}]
116 def COND_NE : PatLeaf <
118 [{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}]
121 def COND_NULL : PatLeaf <
126 //===----------------------------------------------------------------------===//
127 // Load/Store Pattern Fragments
128 //===----------------------------------------------------------------------===//
130 def az_extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
131 LoadSDNode *L = cast<LoadSDNode>(N);
132 return L->getExtensionType() == ISD::ZEXTLOAD ||
133 L->getExtensionType() == ISD::EXTLOAD;
136 def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
137 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
140 def az_extloadi8_global : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
141 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
144 def sextloadi8_global : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
145 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
148 def az_extloadi8_constant : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
149 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
152 def sextloadi8_constant : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
153 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
156 def az_extloadi8_local : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
157 return isLocalLoad(dyn_cast<LoadSDNode>(N));
160 def sextloadi8_local : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
161 return isLocalLoad(dyn_cast<LoadSDNode>(N));
164 def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
165 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
168 def az_extloadi16_global : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
169 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
172 def sextloadi16_global : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
173 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
176 def az_extloadi16_constant : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
177 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
180 def sextloadi16_constant : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
181 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
184 def az_extloadi16_local : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
185 return isLocalLoad(dyn_cast<LoadSDNode>(N));
188 def sextloadi16_local : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
189 return isLocalLoad(dyn_cast<LoadSDNode>(N));
192 def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
193 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
196 def az_extloadi32_global : PatFrag<(ops node:$ptr),
197 (az_extloadi32 node:$ptr), [{
198 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
201 def az_extloadi32_constant : PatFrag<(ops node:$ptr),
202 (az_extloadi32 node:$ptr), [{
203 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
206 def truncstorei8_global : PatFrag<(ops node:$val, node:$ptr),
207 (truncstorei8 node:$val, node:$ptr), [{
208 return isGlobalStore(dyn_cast<StoreSDNode>(N));
211 def truncstorei16_global : PatFrag<(ops node:$val, node:$ptr),
212 (truncstorei16 node:$val, node:$ptr), [{
213 return isGlobalStore(dyn_cast<StoreSDNode>(N));
216 def local_store : PatFrag<(ops node:$val, node:$ptr),
217 (store node:$val, node:$ptr), [{
218 return isLocalStore(dyn_cast<StoreSDNode>(N));
221 def truncstorei8_local : PatFrag<(ops node:$val, node:$ptr),
222 (truncstorei8 node:$val, node:$ptr), [{
223 return isLocalStore(dyn_cast<StoreSDNode>(N));
226 def truncstorei16_local : PatFrag<(ops node:$val, node:$ptr),
227 (truncstorei16 node:$val, node:$ptr), [{
228 return isLocalStore(dyn_cast<StoreSDNode>(N));
231 def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
232 return isLocalLoad(dyn_cast<LoadSDNode>(N));
235 def atomic_load_add_local : PatFrag<(ops node:$ptr, node:$value),
236 (atomic_load_add node:$ptr, node:$value), [{
237 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
240 def atomic_load_sub_local : PatFrag<(ops node:$ptr, node:$value),
241 (atomic_load_sub node:$ptr, node:$value), [{
242 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
245 def mskor_global : PatFrag<(ops node:$val, node:$ptr),
246 (AMDGPUstore_mskor node:$val, node:$ptr), [{
247 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
251 int TWO_PI = 0x40c90fdb;
253 int TWO_PI_INV = 0x3e22f983;
254 int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding
255 int FP32_NEG_ONE = 0xbf800000;
256 int FP32_ONE = 0x3f800000;
258 def CONST : Constants;
260 def FP_ZERO : PatLeaf <
262 [{return N->getValueAPF().isZero();}]
265 def FP_ONE : PatLeaf <
267 [{return N->isExactlyValue(1.0);}]
270 let isCodeGenOnly = 1, isPseudo = 1 in {
272 let usesCustomInserter = 1 in {
274 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
278 [(set f32:$dst, (int_AMDIL_clamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
281 class FABS <RegisterClass rc> : AMDGPUShaderInst <
285 [(set f32:$dst, (fabs f32:$src0))]
288 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
292 [(set f32:$dst, (fneg f32:$src0))]
295 } // usesCustomInserter = 1
297 multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
298 ComplexPattern addrPat> {
299 let UseNamedOperandTable = 1 in {
301 def RegisterLoad : AMDGPUShaderInst <
302 (outs dstClass:$dst),
303 (ins addrClass:$addr, i32imm:$chan),
304 "RegisterLoad $dst, $addr",
305 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]
307 let isRegisterLoad = 1;
310 def RegisterStore : AMDGPUShaderInst <
312 (ins dstClass:$val, addrClass:$addr, i32imm:$chan),
313 "RegisterStore $val, $addr",
314 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]
316 let isRegisterStore = 1;
321 } // End isCodeGenOnly = 1, isPseudo = 1
323 /* Generic helper patterns for intrinsics */
324 /* -------------------------------------- */
326 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
328 (fpow f32:$src0, f32:$src1),
329 (exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
332 /* Other helper patterns */
333 /* --------------------- */
335 /* Extract element pattern */
336 class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
339 (sub_type (vector_extract vec_type:$src, sub_idx)),
340 (EXTRACT_SUBREG $src, sub_reg)
343 /* Insert element pattern */
344 class Insert_Element <ValueType elem_type, ValueType vec_type,
345 int sub_idx, SubRegIndex sub_reg>
347 (vector_insert vec_type:$vec, elem_type:$elem, sub_idx),
348 (INSERT_SUBREG $vec, $elem, sub_reg)
351 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
352 // can handle COPY instructions.
353 // bitconvert pattern
354 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
355 (dt (bitconvert (st rc:$src0))),
359 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
360 // can handle COPY instructions.
361 class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
362 (vt (AMDGPUdwordaddr (vt rc:$addr))),
368 multiclass BFIPatterns <Instruction BFI_INT> {
370 // Definition from ISA doc:
371 // (y & x) | (z & ~x)
373 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
377 // SHA-256 Ch function
380 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
386 // SHA-256 Ma patterns
388 // ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
389 class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
390 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
391 (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
394 // Bitfield extract patterns
398 XXX: The BFE pattern is not working correctly because the XForm is not being
401 def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>;
402 def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}],
403 SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>;
405 class BFEPattern <Instruction BFE> : Pat <
406 (and (srl i32:$x, legalshift32:$y), bfemask:$z),
413 class ROTRPattern <Instruction BIT_ALIGN> : Pat <
414 (rotr i32:$src0, i32:$src1),
415 (BIT_ALIGN $src0, $src0, $src1)
418 // 24-bit arithmetic patterns
419 def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
422 class UMUL24Pattern <Instruction UMUL24> : Pat <
423 (mul U24:$x, U24:$y),
428 class IMad24Pat<Instruction Inst> : Pat <
429 (add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2),
430 (Inst $src0, $src1, $src2)
433 class UMad24Pat<Instruction Inst> : Pat <
434 (add (AMDGPUmul_u24 i32:$src0, i32:$src1), i32:$src2),
435 (Inst $src0, $src1, $src2)
438 multiclass Expand24IBitOps<Instruction MulInst, Instruction AddInst> {
439 def _expand_imad24 : Pat <
440 (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2),
441 (AddInst (MulInst $src0, $src1), $src2)
444 def _expand_imul24 : Pat <
445 (AMDGPUmul_i24 i32:$src0, i32:$src1),
446 (MulInst $src0, $src1)
450 multiclass Expand24UBitOps<Instruction MulInst, Instruction AddInst> {
451 def _expand_umad24 : Pat <
452 (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2),
453 (AddInst (MulInst $src0, $src1), $src2)
456 def _expand_umul24 : Pat <
457 (AMDGPUmul_u24 i32:$src0, i32:$src1),
458 (MulInst $src0, $src1)
462 include "R600Instructions.td"
463 include "R700Instructions.td"
464 include "EvergreenInstructions.td"
465 include "CaymanInstructions.td"
467 include "SIInstrInfo.td"