1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction defs that are common to all hw codegen
13 //===----------------------------------------------------------------------===//
15 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
16 field bit isRegisterLoad = 0;
17 field bit isRegisterStore = 0;
19 let Namespace = "AMDGPU";
20 let OutOperandList = outs;
21 let InOperandList = ins;
23 let Pattern = pattern;
24 let Itinerary = NullALU;
26 let TSFlags{63} = isRegisterLoad;
27 let TSFlags{62} = isRegisterStore;
30 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
31 : AMDGPUInst<outs, ins, asm, pattern> {
33 field bits<32> Inst = 0xffffffff;
37 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
39 def COND_EQ : PatLeaf <
41 [{switch(N->get()){{default: return false;
42 case ISD::SETOEQ: case ISD::SETUEQ:
43 case ISD::SETEQ: return true;}}}]
46 def COND_NE : PatLeaf <
48 [{switch(N->get()){{default: return false;
49 case ISD::SETONE: case ISD::SETUNE:
50 case ISD::SETNE: return true;}}}]
52 def COND_GT : PatLeaf <
54 [{switch(N->get()){{default: return false;
55 case ISD::SETOGT: case ISD::SETUGT:
56 case ISD::SETGT: return true;}}}]
59 def COND_GE : PatLeaf <
61 [{switch(N->get()){{default: return false;
62 case ISD::SETOGE: case ISD::SETUGE:
63 case ISD::SETGE: return true;}}}]
66 def COND_LT : PatLeaf <
68 [{switch(N->get()){{default: return false;
69 case ISD::SETOLT: case ISD::SETULT:
70 case ISD::SETLT: return true;}}}]
73 def COND_LE : PatLeaf <
75 [{switch(N->get()){{default: return false;
76 case ISD::SETOLE: case ISD::SETULE:
77 case ISD::SETLE: return true;}}}]
80 //===----------------------------------------------------------------------===//
81 // Load/Store Pattern Fragments
82 //===----------------------------------------------------------------------===//
84 def zextloadi8_global : PatFrag<(ops node:$ptr), (zextloadi8 node:$ptr), [{
85 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
89 int TWO_PI = 0x40c90fdb;
91 int TWO_PI_INV = 0x3e22f983;
93 def CONST : Constants;
95 def FP_ZERO : PatLeaf <
97 [{return N->getValueAPF().isZero();}]
100 def FP_ONE : PatLeaf <
102 [{return N->isExactlyValue(1.0);}]
105 let isCodeGenOnly = 1, isPseudo = 1 in {
107 let usesCustomInserter = 1 in {
109 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
113 [(set rc:$dst, (int_AMDIL_clamp rc:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
116 class FABS <RegisterClass rc> : AMDGPUShaderInst <
120 [(set rc:$dst, (fabs rc:$src0))]
123 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
127 [(set rc:$dst, (fneg rc:$src0))]
130 def SHADER_TYPE : AMDGPUShaderInst <
134 [(int_AMDGPU_shader_type imm:$type)]
137 } // usesCustomInserter = 1
139 multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
140 ComplexPattern addrPat> {
141 def RegisterLoad : AMDGPUShaderInst <
142 (outs dstClass:$dst),
143 (ins addrClass:$addr, i32imm:$chan),
144 "RegisterLoad $dst, $addr",
145 [(set (i32 dstClass:$dst), (AMDGPUregister_load addrPat:$addr,
148 let isRegisterLoad = 1;
151 def RegisterStore : AMDGPUShaderInst <
153 (ins dstClass:$val, addrClass:$addr, i32imm:$chan),
154 "RegisterStore $val, $addr",
155 [(AMDGPUregister_store (i32 dstClass:$val), addrPat:$addr, (i32 timm:$chan))]
157 let isRegisterStore = 1;
161 } // End isCodeGenOnly = 1, isPseudo = 1
163 /* Generic helper patterns for intrinsics */
164 /* -------------------------------------- */
166 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul,
167 RegisterClass rc> : Pat <
168 (fpow rc:$src0, rc:$src1),
169 (exp_ieee (mul rc:$src1, (log_ieee rc:$src0)))
172 /* Other helper patterns */
173 /* --------------------- */
175 /* Extract element pattern */
176 class Extract_Element <ValueType sub_type, ValueType vec_type,
177 RegisterClass vec_class, int sub_idx,
178 SubRegIndex sub_reg>: Pat<
179 (sub_type (vector_extract (vec_type vec_class:$src), sub_idx)),
180 (EXTRACT_SUBREG vec_class:$src, sub_reg)
183 /* Insert element pattern */
184 class Insert_Element <ValueType elem_type, ValueType vec_type,
185 RegisterClass elem_class, RegisterClass vec_class,
186 int sub_idx, SubRegIndex sub_reg> : Pat <
188 (vec_type (vector_insert (vec_type vec_class:$vec),
189 (elem_type elem_class:$elem), sub_idx)),
190 (INSERT_SUBREG vec_class:$vec, elem_class:$elem, sub_reg)
193 // Vector Build pattern
194 class Vector_Build <ValueType vecType, RegisterClass vectorClass,
195 ValueType elemType, RegisterClass elemClass> : Pat <
196 (vecType (build_vector (elemType elemClass:$x), (elemType elemClass:$y),
197 (elemType elemClass:$z), (elemType elemClass:$w))),
198 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
199 (vecType (IMPLICIT_DEF)), elemClass:$x, sel_x), elemClass:$y, sel_y),
200 elemClass:$z, sel_z), elemClass:$w, sel_w)
203 // bitconvert pattern
204 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
205 (dt (bitconvert (st rc:$src0))),
209 class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
210 (vt (AMDGPUdwordaddr (vt rc:$addr))),
214 include "R600Instructions.td"
216 include "SIInstrInfo.td"