1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction defs that are common to all hw codegen
13 //===----------------------------------------------------------------------===//
15 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
16 field bit isRegisterLoad = 0;
17 field bit isRegisterStore = 0;
19 let Namespace = "AMDGPU";
20 let OutOperandList = outs;
21 let InOperandList = ins;
23 let Pattern = pattern;
24 let Itinerary = NullALU;
26 let TSFlags{63} = isRegisterLoad;
27 let TSFlags{62} = isRegisterStore;
30 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
31 : AMDGPUInst<outs, ins, asm, pattern> {
33 field bits<32> Inst = 0xffffffff;
37 def FP32Denormals : Predicate<"Subtarget.hasFP32Denormals()">;
38 def FP64Denormals : Predicate<"Subtarget.hasFP64Denormals()">;
40 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
41 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
43 def u32imm : Operand<i32> {
44 let PrintMethod = "printU32ImmOperand";
47 def u16imm : Operand<i16> {
48 let PrintMethod = "printU16ImmOperand";
51 def u8imm : Operand<i8> {
52 let PrintMethod = "printU8ImmOperand";
55 //===--------------------------------------------------------------------===//
57 //===--------------------------------------------------------------------===//
58 def brtarget : Operand<OtherVT>;
60 //===----------------------------------------------------------------------===//
61 // PatLeafs for floating-point comparisons
62 //===----------------------------------------------------------------------===//
64 def COND_OEQ : PatLeaf <
66 [{return N->get() == ISD::SETOEQ || N->get() == ISD::SETEQ;}]
69 def COND_OGT : PatLeaf <
71 [{return N->get() == ISD::SETOGT || N->get() == ISD::SETGT;}]
74 def COND_OGE : PatLeaf <
76 [{return N->get() == ISD::SETOGE || N->get() == ISD::SETGE;}]
79 def COND_OLT : PatLeaf <
81 [{return N->get() == ISD::SETOLT || N->get() == ISD::SETLT;}]
84 def COND_OLE : PatLeaf <
86 [{return N->get() == ISD::SETOLE || N->get() == ISD::SETLE;}]
89 def COND_UNE : PatLeaf <
91 [{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
94 def COND_O : PatLeaf <(cond), [{return N->get() == ISD::SETO;}]>;
95 def COND_UO : PatLeaf <(cond), [{return N->get() == ISD::SETUO;}]>;
97 //===----------------------------------------------------------------------===//
98 // PatLeafs for unsigned comparisons
99 //===----------------------------------------------------------------------===//
101 def COND_UGT : PatLeaf <(cond), [{return N->get() == ISD::SETUGT;}]>;
102 def COND_UGE : PatLeaf <(cond), [{return N->get() == ISD::SETUGE;}]>;
103 def COND_ULT : PatLeaf <(cond), [{return N->get() == ISD::SETULT;}]>;
104 def COND_ULE : PatLeaf <(cond), [{return N->get() == ISD::SETULE;}]>;
106 //===----------------------------------------------------------------------===//
107 // PatLeafs for signed comparisons
108 //===----------------------------------------------------------------------===//
110 def COND_SGT : PatLeaf <(cond), [{return N->get() == ISD::SETGT;}]>;
111 def COND_SGE : PatLeaf <(cond), [{return N->get() == ISD::SETGE;}]>;
112 def COND_SLT : PatLeaf <(cond), [{return N->get() == ISD::SETLT;}]>;
113 def COND_SLE : PatLeaf <(cond), [{return N->get() == ISD::SETLE;}]>;
115 //===----------------------------------------------------------------------===//
116 // PatLeafs for integer equality
117 //===----------------------------------------------------------------------===//
119 def COND_EQ : PatLeaf <
121 [{return N->get() == ISD::SETEQ || N->get() == ISD::SETUEQ;}]
124 def COND_NE : PatLeaf <
126 [{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}]
129 def COND_NULL : PatLeaf <
134 //===----------------------------------------------------------------------===//
135 // Load/Store Pattern Fragments
136 //===----------------------------------------------------------------------===//
138 def global_store : PatFrag<(ops node:$val, node:$ptr),
139 (store node:$val, node:$ptr), [{
140 return isGlobalStore(dyn_cast<StoreSDNode>(N));
143 // Global address space loads
144 def global_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
145 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
148 // Constant address space loads
149 def constant_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
150 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
153 def az_extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
154 LoadSDNode *L = cast<LoadSDNode>(N);
155 return L->getExtensionType() == ISD::ZEXTLOAD ||
156 L->getExtensionType() == ISD::EXTLOAD;
159 def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
160 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
163 def az_extloadi8_global : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
164 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
167 def sextloadi8_global : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
168 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
171 def az_extloadi8_constant : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
172 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
175 def sextloadi8_constant : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
176 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
179 def az_extloadi8_local : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
180 return isLocalLoad(dyn_cast<LoadSDNode>(N));
183 def sextloadi8_local : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
184 return isLocalLoad(dyn_cast<LoadSDNode>(N));
187 def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
188 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
191 def az_extloadi16_global : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
192 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
195 def sextloadi16_global : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
196 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
199 def az_extloadi16_constant : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
200 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
203 def sextloadi16_constant : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
204 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
207 def az_extloadi16_local : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
208 return isLocalLoad(dyn_cast<LoadSDNode>(N));
211 def sextloadi16_local : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
212 return isLocalLoad(dyn_cast<LoadSDNode>(N));
215 def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
216 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
219 def az_extloadi32_global : PatFrag<(ops node:$ptr),
220 (az_extloadi32 node:$ptr), [{
221 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
224 def az_extloadi32_constant : PatFrag<(ops node:$ptr),
225 (az_extloadi32 node:$ptr), [{
226 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
229 def truncstorei8_global : PatFrag<(ops node:$val, node:$ptr),
230 (truncstorei8 node:$val, node:$ptr), [{
231 return isGlobalStore(dyn_cast<StoreSDNode>(N));
234 def truncstorei16_global : PatFrag<(ops node:$val, node:$ptr),
235 (truncstorei16 node:$val, node:$ptr), [{
236 return isGlobalStore(dyn_cast<StoreSDNode>(N));
239 def local_store : PatFrag<(ops node:$val, node:$ptr),
240 (store node:$val, node:$ptr), [{
241 return isLocalStore(dyn_cast<StoreSDNode>(N));
244 def truncstorei8_local : PatFrag<(ops node:$val, node:$ptr),
245 (truncstorei8 node:$val, node:$ptr), [{
246 return isLocalStore(dyn_cast<StoreSDNode>(N));
249 def truncstorei16_local : PatFrag<(ops node:$val, node:$ptr),
250 (truncstorei16 node:$val, node:$ptr), [{
251 return isLocalStore(dyn_cast<StoreSDNode>(N));
254 def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
255 return isLocalLoad(dyn_cast<LoadSDNode>(N));
259 class local_binary_atomic_op<SDNode atomic_op> :
260 PatFrag<(ops node:$ptr, node:$value),
261 (atomic_op node:$ptr, node:$value), [{
262 return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
266 def atomic_swap_local : local_binary_atomic_op<atomic_swap>;
267 def atomic_load_add_local : local_binary_atomic_op<atomic_load_add>;
268 def atomic_load_sub_local : local_binary_atomic_op<atomic_load_sub>;
269 def atomic_load_and_local : local_binary_atomic_op<atomic_load_and>;
270 def atomic_load_or_local : local_binary_atomic_op<atomic_load_or>;
271 def atomic_load_xor_local : local_binary_atomic_op<atomic_load_xor>;
272 def atomic_load_nand_local : local_binary_atomic_op<atomic_load_nand>;
273 def atomic_load_min_local : local_binary_atomic_op<atomic_load_min>;
274 def atomic_load_max_local : local_binary_atomic_op<atomic_load_max>;
275 def atomic_load_umin_local : local_binary_atomic_op<atomic_load_umin>;
276 def atomic_load_umax_local : local_binary_atomic_op<atomic_load_umax>;
278 def mskor_global : PatFrag<(ops node:$val, node:$ptr),
279 (AMDGPUstore_mskor node:$val, node:$ptr), [{
280 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
283 def atomic_cmp_swap_32_local :
284 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
285 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
286 AtomicSDNode *AN = cast<AtomicSDNode>(N);
287 return AN->getMemoryVT() == MVT::i32 &&
288 AN->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
291 def atomic_cmp_swap_64_local :
292 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
293 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
294 AtomicSDNode *AN = cast<AtomicSDNode>(N);
295 return AN->getMemoryVT() == MVT::i64 &&
296 AN->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
301 int TWO_PI = 0x40c90fdb;
303 int TWO_PI_INV = 0x3e22f983;
304 int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding
305 int FP32_NEG_ONE = 0xbf800000;
306 int FP32_ONE = 0x3f800000;
308 def CONST : Constants;
310 def FP_ZERO : PatLeaf <
312 [{return N->getValueAPF().isZero();}]
315 def FP_ONE : PatLeaf <
317 [{return N->isExactlyValue(1.0);}]
320 let isCodeGenOnly = 1, isPseudo = 1 in {
322 let usesCustomInserter = 1 in {
324 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
328 [(set f32:$dst, (AMDGPUclamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
331 class FABS <RegisterClass rc> : AMDGPUShaderInst <
335 [(set f32:$dst, (fabs f32:$src0))]
338 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
342 [(set f32:$dst, (fneg f32:$src0))]
345 } // usesCustomInserter = 1
347 multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
348 ComplexPattern addrPat> {
349 let UseNamedOperandTable = 1 in {
351 def RegisterLoad : AMDGPUShaderInst <
352 (outs dstClass:$dst),
353 (ins addrClass:$addr, i32imm:$chan),
354 "RegisterLoad $dst, $addr",
355 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]
357 let isRegisterLoad = 1;
360 def RegisterStore : AMDGPUShaderInst <
362 (ins dstClass:$val, addrClass:$addr, i32imm:$chan),
363 "RegisterStore $val, $addr",
364 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]
366 let isRegisterStore = 1;
371 } // End isCodeGenOnly = 1, isPseudo = 1
373 /* Generic helper patterns for intrinsics */
374 /* -------------------------------------- */
376 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
378 (fpow f32:$src0, f32:$src1),
379 (exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
382 /* Other helper patterns */
383 /* --------------------- */
385 /* Extract element pattern */
386 class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
389 (sub_type (vector_extract vec_type:$src, sub_idx)),
390 (EXTRACT_SUBREG $src, sub_reg)
393 /* Insert element pattern */
394 class Insert_Element <ValueType elem_type, ValueType vec_type,
395 int sub_idx, SubRegIndex sub_reg>
397 (vector_insert vec_type:$vec, elem_type:$elem, sub_idx),
398 (INSERT_SUBREG $vec, $elem, sub_reg)
401 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
402 // can handle COPY instructions.
403 // bitconvert pattern
404 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
405 (dt (bitconvert (st rc:$src0))),
409 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
410 // can handle COPY instructions.
411 class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
412 (vt (AMDGPUdwordaddr (vt rc:$addr))),
418 multiclass BFIPatterns <Instruction BFI_INT, Instruction LoadImm32> {
420 // Definition from ISA doc:
421 // (y & x) | (z & ~x)
423 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
427 // SHA-256 Ch function
430 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
435 (fcopysign f32:$src0, f32:$src1),
436 (BFI_INT (LoadImm32 0x7fffffff), $src0, $src1)
440 (f64 (fcopysign f64:$src0, f64:$src1)),
441 (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
442 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0),
443 (BFI_INT (LoadImm32 0x7fffffff),
444 (i32 (EXTRACT_SUBREG $src0, sub1)),
445 (i32 (EXTRACT_SUBREG $src1, sub1))), sub1)
449 // SHA-256 Ma patterns
451 // ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
452 class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
453 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
454 (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
457 // Bitfield extract patterns
461 XXX: The BFE pattern is not working correctly because the XForm is not being
464 def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>;
465 def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}],
466 SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>;
468 class BFEPattern <Instruction BFE> : Pat <
469 (and (srl i32:$x, legalshift32:$y), bfemask:$z),
476 class ROTRPattern <Instruction BIT_ALIGN> : Pat <
477 (rotr i32:$src0, i32:$src1),
478 (BIT_ALIGN $src0, $src0, $src1)
481 // 24-bit arithmetic patterns
482 def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
485 class UMUL24Pattern <Instruction UMUL24> : Pat <
486 (mul U24:$x, U24:$y),
491 class IMad24Pat<Instruction Inst> : Pat <
492 (add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2),
493 (Inst $src0, $src1, $src2)
496 class UMad24Pat<Instruction Inst> : Pat <
497 (add (AMDGPUmul_u24 i32:$src0, i32:$src1), i32:$src2),
498 (Inst $src0, $src1, $src2)
501 multiclass Expand24IBitOps<Instruction MulInst, Instruction AddInst> {
502 def _expand_imad24 : Pat <
503 (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2),
504 (AddInst (MulInst $src0, $src1), $src2)
507 def _expand_imul24 : Pat <
508 (AMDGPUmul_i24 i32:$src0, i32:$src1),
509 (MulInst $src0, $src1)
513 multiclass Expand24UBitOps<Instruction MulInst, Instruction AddInst> {
514 def _expand_umad24 : Pat <
515 (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2),
516 (AddInst (MulInst $src0, $src1), $src2)
519 def _expand_umul24 : Pat <
520 (AMDGPUmul_u24 i32:$src0, i32:$src1),
521 (MulInst $src0, $src1)
525 class RcpPat<Instruction RcpInst, ValueType vt> : Pat <
526 (fdiv FP_ONE, vt:$src),
530 multiclass RsqPat<Instruction RsqInst, ValueType vt> {
532 (fdiv FP_ONE, (fsqrt vt:$src)),
537 (AMDGPUrcp (fsqrt vt:$src)),
542 include "R600Instructions.td"
543 include "R700Instructions.td"
544 include "EvergreenInstructions.td"
545 include "CaymanInstructions.td"
547 include "SIInstrInfo.td"