1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction defs that are common to all hw codegen
13 //===----------------------------------------------------------------------===//
15 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
16 field bit isRegisterLoad = 0;
17 field bit isRegisterStore = 0;
19 let Namespace = "AMDGPU";
20 let OutOperandList = outs;
21 let InOperandList = ins;
23 let Pattern = pattern;
24 let Itinerary = NullALU;
26 let TSFlags{63} = isRegisterLoad;
27 let TSFlags{62} = isRegisterStore;
30 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
31 : AMDGPUInst<outs, ins, asm, pattern> {
33 field bits<32> Inst = 0xffffffff;
37 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
39 def COND_EQ : PatLeaf <
41 [{switch(N->get()){{default: return false;
42 case ISD::SETOEQ: case ISD::SETUEQ:
43 case ISD::SETEQ: return true;}}}]
46 def COND_NE : PatLeaf <
48 [{switch(N->get()){{default: return false;
49 case ISD::SETONE: case ISD::SETUNE:
50 case ISD::SETNE: return true;}}}]
52 def COND_GT : PatLeaf <
54 [{switch(N->get()){{default: return false;
55 case ISD::SETOGT: case ISD::SETUGT:
56 case ISD::SETGT: return true;}}}]
59 def COND_GE : PatLeaf <
61 [{switch(N->get()){{default: return false;
62 case ISD::SETOGE: case ISD::SETUGE:
63 case ISD::SETGE: return true;}}}]
66 def COND_LT : PatLeaf <
68 [{switch(N->get()){{default: return false;
69 case ISD::SETOLT: case ISD::SETULT:
70 case ISD::SETLT: return true;}}}]
73 def COND_LE : PatLeaf <
75 [{switch(N->get()){{default: return false;
76 case ISD::SETOLE: case ISD::SETULE:
77 case ISD::SETLE: return true;}}}]
80 def COND_NULL : PatLeaf <
85 //===----------------------------------------------------------------------===//
86 // Load/Store Pattern Fragments
87 //===----------------------------------------------------------------------===//
89 def zextloadi8_global : PatFrag<(ops node:$ptr), (zextloadi8 node:$ptr), [{
90 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
94 int TWO_PI = 0x40c90fdb;
96 int TWO_PI_INV = 0x3e22f983;
97 int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding
99 def CONST : Constants;
101 def FP_ZERO : PatLeaf <
103 [{return N->getValueAPF().isZero();}]
106 def FP_ONE : PatLeaf <
108 [{return N->isExactlyValue(1.0);}]
111 let isCodeGenOnly = 1, isPseudo = 1 in {
113 let usesCustomInserter = 1 in {
115 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
119 [(set rc:$dst, (int_AMDIL_clamp rc:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
122 class FABS <RegisterClass rc> : AMDGPUShaderInst <
126 [(set rc:$dst, (fabs rc:$src0))]
129 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
133 [(set rc:$dst, (fneg rc:$src0))]
136 } // usesCustomInserter = 1
138 multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
139 ComplexPattern addrPat> {
140 def RegisterLoad : AMDGPUShaderInst <
141 (outs dstClass:$dst),
142 (ins addrClass:$addr, i32imm:$chan),
143 "RegisterLoad $dst, $addr",
144 [(set (i32 dstClass:$dst), (AMDGPUregister_load addrPat:$addr,
147 let isRegisterLoad = 1;
150 def RegisterStore : AMDGPUShaderInst <
152 (ins dstClass:$val, addrClass:$addr, i32imm:$chan),
153 "RegisterStore $val, $addr",
154 [(AMDGPUregister_store (i32 dstClass:$val), addrPat:$addr, (i32 timm:$chan))]
156 let isRegisterStore = 1;
160 } // End isCodeGenOnly = 1, isPseudo = 1
162 /* Generic helper patterns for intrinsics */
163 /* -------------------------------------- */
165 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul,
166 RegisterClass rc> : Pat <
167 (fpow rc:$src0, rc:$src1),
168 (exp_ieee (mul rc:$src1, (log_ieee rc:$src0)))
171 /* Other helper patterns */
172 /* --------------------- */
174 /* Extract element pattern */
175 class Extract_Element <ValueType sub_type, ValueType vec_type,
176 RegisterClass vec_class, int sub_idx,
177 SubRegIndex sub_reg>: Pat<
178 (sub_type (vector_extract (vec_type vec_class:$src), sub_idx)),
179 (EXTRACT_SUBREG vec_class:$src, sub_reg)
182 /* Insert element pattern */
183 class Insert_Element <ValueType elem_type, ValueType vec_type,
184 RegisterClass elem_class, RegisterClass vec_class,
185 int sub_idx, SubRegIndex sub_reg> : Pat <
187 (vec_type (vector_insert (vec_type vec_class:$vec),
188 (elem_type elem_class:$elem), sub_idx)),
189 (INSERT_SUBREG vec_class:$vec, elem_class:$elem, sub_reg)
192 // Vector Build pattern
193 class Vector1_Build <ValueType vecType, RegisterClass vectorClass,
194 ValueType elemType, RegisterClass elemClass> : Pat <
195 (vecType (build_vector (elemType elemClass:$src))),
196 (vecType elemClass:$src)
199 class Vector2_Build <ValueType vecType, RegisterClass vectorClass,
200 ValueType elemType, RegisterClass elemClass> : Pat <
201 (vecType (build_vector (elemType elemClass:$sub0), (elemType elemClass:$sub1))),
202 (INSERT_SUBREG (INSERT_SUBREG
203 (vecType (IMPLICIT_DEF)), elemClass:$sub0, sub0), elemClass:$sub1, sub1)
206 class Vector4_Build <ValueType vecType, RegisterClass vectorClass,
207 ValueType elemType, RegisterClass elemClass> : Pat <
208 (vecType (build_vector (elemType elemClass:$x), (elemType elemClass:$y),
209 (elemType elemClass:$z), (elemType elemClass:$w))),
210 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
211 (vecType (IMPLICIT_DEF)), elemClass:$x, sub0), elemClass:$y, sub1),
212 elemClass:$z, sub2), elemClass:$w, sub3)
215 class Vector8_Build <ValueType vecType, RegisterClass vectorClass,
216 ValueType elemType, RegisterClass elemClass> : Pat <
217 (vecType (build_vector (elemType elemClass:$sub0), (elemType elemClass:$sub1),
218 (elemType elemClass:$sub2), (elemType elemClass:$sub3),
219 (elemType elemClass:$sub4), (elemType elemClass:$sub5),
220 (elemType elemClass:$sub6), (elemType elemClass:$sub7))),
221 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
222 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
223 (vecType (IMPLICIT_DEF)), elemClass:$sub0, sub0), elemClass:$sub1, sub1),
224 elemClass:$sub2, sub2), elemClass:$sub3, sub3),
225 elemClass:$sub4, sub4), elemClass:$sub5, sub5),
226 elemClass:$sub6, sub6), elemClass:$sub7, sub7)
229 class Vector16_Build <ValueType vecType, RegisterClass vectorClass,
230 ValueType elemType, RegisterClass elemClass> : Pat <
231 (vecType (build_vector (elemType elemClass:$sub0), (elemType elemClass:$sub1),
232 (elemType elemClass:$sub2), (elemType elemClass:$sub3),
233 (elemType elemClass:$sub4), (elemType elemClass:$sub5),
234 (elemType elemClass:$sub6), (elemType elemClass:$sub7),
235 (elemType elemClass:$sub8), (elemType elemClass:$sub9),
236 (elemType elemClass:$sub10), (elemType elemClass:$sub11),
237 (elemType elemClass:$sub12), (elemType elemClass:$sub13),
238 (elemType elemClass:$sub14), (elemType elemClass:$sub15))),
239 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
240 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
241 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
242 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
243 (vecType (IMPLICIT_DEF)), elemClass:$sub0, sub0), elemClass:$sub1, sub1),
244 elemClass:$sub2, sub2), elemClass:$sub3, sub3),
245 elemClass:$sub4, sub4), elemClass:$sub5, sub5),
246 elemClass:$sub6, sub6), elemClass:$sub7, sub7),
247 elemClass:$sub8, sub8), elemClass:$sub9, sub9),
248 elemClass:$sub10, sub10), elemClass:$sub11, sub11),
249 elemClass:$sub12, sub12), elemClass:$sub13, sub13),
250 elemClass:$sub14, sub14), elemClass:$sub15, sub15)
253 // bitconvert pattern
254 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
255 (dt (bitconvert (st rc:$src0))),
259 class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
260 (vt (AMDGPUdwordaddr (vt rc:$addr))),
266 multiclass BFIPatterns <Instruction BFI_INT> {
268 // Definition from ISA doc:
269 // (y & x) | (z & ~x)
271 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
275 // SHA-256 Ch function
278 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
284 include "R600Instructions.td"
286 include "SIInstrInfo.td"