1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction defs that are common to all hw codegen
13 //===----------------------------------------------------------------------===//
15 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
16 field bit isRegisterLoad = 0;
17 field bit isRegisterStore = 0;
19 let Namespace = "AMDGPU";
20 let OutOperandList = outs;
21 let InOperandList = ins;
23 let Pattern = pattern;
24 let Itinerary = NullALU;
26 let TSFlags{63} = isRegisterLoad;
27 let TSFlags{62} = isRegisterStore;
30 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
31 : AMDGPUInst<outs, ins, asm, pattern> {
33 field bits<32> Inst = 0xffffffff;
37 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
38 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
40 def COND_EQ : PatLeaf <
42 [{switch(N->get()){{default: return false;
43 case ISD::SETOEQ: case ISD::SETUEQ:
44 case ISD::SETEQ: return true;}}}]
47 def COND_OEQ : PatLeaf <
49 [{return N->get() == ISD::SETOEQ || N->get() == ISD::SETEQ;}]
52 def COND_NE : PatLeaf <
54 [{switch(N->get()){{default: return false;
55 case ISD::SETONE: case ISD::SETUNE:
56 case ISD::SETNE: return true;}}}]
59 def COND_UNE : PatLeaf <
61 [{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
64 def COND_GT : PatLeaf <
66 [{switch(N->get()){{default: return false;
67 case ISD::SETOGT: case ISD::SETUGT:
68 case ISD::SETGT: return true;}}}]
71 def COND_OGT : PatLeaf <
73 [{return N->get() == ISD::SETOGT || N->get() == ISD::SETGT;}]
76 def COND_GE : PatLeaf <
78 [{switch(N->get()){{default: return false;
79 case ISD::SETOGE: case ISD::SETUGE:
80 case ISD::SETGE: return true;}}}]
83 def COND_OGE : PatLeaf <
85 [{return N->get() == ISD::SETOGE || N->get() == ISD::SETGE;}]
88 def COND_LT : PatLeaf <
90 [{switch(N->get()){{default: return false;
91 case ISD::SETOLT: case ISD::SETULT:
92 case ISD::SETLT: return true;}}}]
95 def COND_LE : PatLeaf <
97 [{switch(N->get()){{default: return false;
98 case ISD::SETOLE: case ISD::SETULE:
99 case ISD::SETLE: return true;}}}]
102 def COND_NULL : PatLeaf <
107 //===----------------------------------------------------------------------===//
108 // Load/Store Pattern Fragments
109 //===----------------------------------------------------------------------===//
111 def az_extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
112 LoadSDNode *L = cast<LoadSDNode>(N);
113 return L->getExtensionType() == ISD::ZEXTLOAD ||
114 L->getExtensionType() == ISD::EXTLOAD;
117 def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
118 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
121 def az_extloadi8_global : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
122 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
125 def sextloadi8_global : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
126 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
129 def az_extloadi8_constant : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
130 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
133 def sextloadi8_constant : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
134 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
137 def az_extloadi8_local : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
138 return isLocalLoad(dyn_cast<LoadSDNode>(N));
141 def sextloadi8_local : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
142 return isLocalLoad(dyn_cast<LoadSDNode>(N));
145 def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
146 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
149 def az_extloadi16_global : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
150 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
153 def sextloadi16_global : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
154 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
157 def az_extloadi16_constant : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
158 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
161 def sextloadi16_constant : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
162 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
165 def az_extloadi16_local : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
166 return isLocalLoad(dyn_cast<LoadSDNode>(N));
169 def sextloadi16_local : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
170 return isLocalLoad(dyn_cast<LoadSDNode>(N));
173 def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
174 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
177 def az_extloadi32_global : PatFrag<(ops node:$ptr),
178 (az_extloadi32 node:$ptr), [{
179 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
182 def az_extloadi32_constant : PatFrag<(ops node:$ptr),
183 (az_extloadi32 node:$ptr), [{
184 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
187 def truncstorei8_global : PatFrag<(ops node:$val, node:$ptr),
188 (truncstorei8 node:$val, node:$ptr), [{
189 return isGlobalStore(dyn_cast<StoreSDNode>(N));
192 def truncstorei16_global : PatFrag<(ops node:$val, node:$ptr),
193 (truncstorei16 node:$val, node:$ptr), [{
194 return isGlobalStore(dyn_cast<StoreSDNode>(N));
197 def local_store : PatFrag<(ops node:$val, node:$ptr),
198 (store node:$val, node:$ptr), [{
199 return isLocalStore(dyn_cast<StoreSDNode>(N));
202 def truncstorei8_local : PatFrag<(ops node:$val, node:$ptr),
203 (truncstorei8 node:$val, node:$ptr), [{
204 return isLocalStore(dyn_cast<StoreSDNode>(N));
207 def truncstorei16_local : PatFrag<(ops node:$val, node:$ptr),
208 (truncstorei16 node:$val, node:$ptr), [{
209 return isLocalStore(dyn_cast<StoreSDNode>(N));
212 def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
213 return isLocalLoad(dyn_cast<LoadSDNode>(N));
216 def atomic_load_add_local : PatFrag<(ops node:$ptr, node:$value),
217 (atomic_load_add node:$ptr, node:$value), [{
218 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
221 def atomic_load_sub_local : PatFrag<(ops node:$ptr, node:$value),
222 (atomic_load_sub node:$ptr, node:$value), [{
223 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
226 def mskor_global : PatFrag<(ops node:$val, node:$ptr),
227 (AMDGPUstore_mskor node:$val, node:$ptr), [{
228 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
232 int TWO_PI = 0x40c90fdb;
234 int TWO_PI_INV = 0x3e22f983;
235 int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding
237 def CONST : Constants;
239 def FP_ZERO : PatLeaf <
241 [{return N->getValueAPF().isZero();}]
244 def FP_ONE : PatLeaf <
246 [{return N->isExactlyValue(1.0);}]
249 def U24 : ComplexPattern<i32, 1, "SelectU24", [], []>;
250 def I24 : ComplexPattern<i32, 1, "SelectI24", [], []>;
252 let isCodeGenOnly = 1, isPseudo = 1 in {
254 let usesCustomInserter = 1 in {
256 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
260 [(set f32:$dst, (int_AMDIL_clamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
263 class FABS <RegisterClass rc> : AMDGPUShaderInst <
267 [(set f32:$dst, (fabs f32:$src0))]
270 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
274 [(set f32:$dst, (fneg f32:$src0))]
277 } // usesCustomInserter = 1
279 multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
280 ComplexPattern addrPat> {
281 let UseNamedOperandTable = 1 in {
283 def RegisterLoad : AMDGPUShaderInst <
284 (outs dstClass:$dst),
285 (ins addrClass:$addr, i32imm:$chan),
286 "RegisterLoad $dst, $addr",
287 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]
289 let isRegisterLoad = 1;
292 def RegisterStore : AMDGPUShaderInst <
294 (ins dstClass:$val, addrClass:$addr, i32imm:$chan),
295 "RegisterStore $val, $addr",
296 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]
298 let isRegisterStore = 1;
303 } // End isCodeGenOnly = 1, isPseudo = 1
305 /* Generic helper patterns for intrinsics */
306 /* -------------------------------------- */
308 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
310 (fpow f32:$src0, f32:$src1),
311 (exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
314 /* Other helper patterns */
315 /* --------------------- */
317 /* Extract element pattern */
318 class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
321 (sub_type (vector_extract vec_type:$src, sub_idx)),
322 (EXTRACT_SUBREG $src, sub_reg)
325 /* Insert element pattern */
326 class Insert_Element <ValueType elem_type, ValueType vec_type,
327 int sub_idx, SubRegIndex sub_reg>
329 (vector_insert vec_type:$vec, elem_type:$elem, sub_idx),
330 (INSERT_SUBREG $vec, $elem, sub_reg)
333 class Vector4_Build <ValueType vecType, ValueType elemType> : Pat <
334 (vecType (build_vector elemType:$x, elemType:$y, elemType:$z, elemType:$w)),
335 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
336 (vecType (IMPLICIT_DEF)), $x, sub0), $y, sub1), $z, sub2), $w, sub3)
339 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
340 // can handle COPY instructions.
341 // bitconvert pattern
342 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
343 (dt (bitconvert (st rc:$src0))),
347 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
348 // can handle COPY instructions.
349 class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
350 (vt (AMDGPUdwordaddr (vt rc:$addr))),
356 multiclass BFIPatterns <Instruction BFI_INT> {
358 // Definition from ISA doc:
359 // (y & x) | (z & ~x)
361 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
365 // SHA-256 Ch function
368 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
374 // SHA-256 Ma patterns
376 // ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
377 class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
378 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
379 (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
382 // Bitfield extract patterns
384 def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>;
385 def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}],
386 SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>;
388 class BFEPattern <Instruction BFE> : Pat <
389 (and (srl i32:$x, legalshift32:$y), bfemask:$z),
394 class ROTRPattern <Instruction BIT_ALIGN> : Pat <
395 (rotr i32:$src0, i32:$src1),
396 (BIT_ALIGN $src0, $src0, $src1)
399 // 24-bit arithmetic patterns
400 def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
403 class UMUL24Pattern <Instruction UMUL24> : Pat <
404 (mul U24:$x, U24:$y),
409 include "R600Instructions.td"
411 include "SIInstrInfo.td"