1 //===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains DAG node defintions for the AMDGPU target.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // AMDGPU DAG Profiles
16 //===----------------------------------------------------------------------===//
18 def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
19 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
22 //===----------------------------------------------------------------------===//
26 // This argument to this node is a dword address.
27 def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
30 def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
32 // out = max(a, b) a and b are floats
33 def AMDGPUfmax : SDNode<"AMDGPUISD::FMAX", SDTFPBinOp,
34 [SDNPCommutative, SDNPAssociative]
37 def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPTernaryOp, []>;
39 // out = max(a, b) a and b are signed ints
40 def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
41 [SDNPCommutative, SDNPAssociative]
44 // out = max(a, b) a and b are unsigned ints
45 def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
46 [SDNPCommutative, SDNPAssociative]
49 // out = min(a, b) a and b are floats
50 def AMDGPUfmin : SDNode<"AMDGPUISD::FMIN", SDTFPBinOp,
51 [SDNPCommutative, SDNPAssociative]
54 // out = min(a, b) a snd b are signed ints
55 def AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp,
56 [SDNPCommutative, SDNPAssociative]
59 // out = min(a, b) a and b are unsigned ints
60 def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
61 [SDNPCommutative, SDNPAssociative]
65 def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
67 def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
69 def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
71 def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
75 // urecip - This operation is a helper for integer division, it returns the
76 // result of 1 / a as a fractional unsigned integer.
77 // out = (2^32 / a) + e
78 // e is rounding error
79 def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
81 def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
82 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
83 [SDNPHasChain, SDNPMayLoad]>;
85 def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
86 SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
87 [SDNPHasChain, SDNPMayStore]>;
89 // MSKOR instructions are atomic memory instructions used mainly for storing
90 // 8-bit and 16-bit values. The definition is:
92 // MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
94 // src0: vec4(src, 0, 0, mask)
95 // src1: dst - rat offset (aka pointer) in dwords
96 def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
97 SDTypeProfile<0, 2, []>,
98 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
100 def AMDGPUround : SDNode<"ISD::FROUND",
101 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
103 def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
104 def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
105 def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
106 def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
108 // Signed and unsigned 24-bit mulitply. The highest 8-bits are ignore when
109 // performing the mulitply. The result is a 32-bit value.
110 def AMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
113 def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
117 def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
120 def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
124 //===----------------------------------------------------------------------===//
125 // Flow Control Profile Types
126 //===----------------------------------------------------------------------===//
127 // Branch instruction where second and third are basic blocks
128 def SDTIL_BRCond : SDTypeProfile<0, 2, [
132 //===----------------------------------------------------------------------===//
133 // Flow Control DAG Nodes
134 //===----------------------------------------------------------------------===//
135 def IL_brcond : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
137 //===----------------------------------------------------------------------===//
138 // Call/Return DAG Nodes
139 //===----------------------------------------------------------------------===//
140 def IL_retflag : SDNode<"AMDGPUISD::RET_FLAG", SDTNone,
141 [SDNPHasChain, SDNPOptInGlue]>;