1 //===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains DAG node defintions for the AMDGPU target.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // AMDGPU DAG Profiles
16 //===----------------------------------------------------------------------===//
18 def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
19 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
22 def AMDGPUTrigPreOp : SDTypeProfile<1, 2,
23 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
26 def AMDGPULdExpOp : SDTypeProfile<1, 2,
27 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
30 def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
31 [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
34 //===----------------------------------------------------------------------===//
38 // This argument to this node is a dword address.
39 def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
41 def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
42 def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
45 def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
48 def AMDGPUrcp : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
50 // out = 1.0 / sqrt(a)
51 def AMDGPUrsq : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
53 // out = 1.0 / sqrt(a)
54 def AMDGPUrsq_legacy : SDNode<"AMDGPUISD::RSQ_LEGACY", SDTFPUnaryOp>;
56 // out = 1.0 / sqrt(a) result clamped to +/- max_float.
57 def AMDGPUrsq_clamped : SDNode<"AMDGPUISD::RSQ_CLAMPED", SDTFPUnaryOp>;
59 def AMDGPUldexp : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
61 // out = max(a, b) a and b are floats
62 def AMDGPUfmax : SDNode<"AMDGPUISD::FMAX", SDTFPBinOp,
63 [SDNPCommutative, SDNPAssociative]
66 def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPTernaryOp, []>;
68 // out = max(a, b) a and b are signed ints
69 def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
70 [SDNPCommutative, SDNPAssociative]
73 // out = max(a, b) a and b are unsigned ints
74 def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
75 [SDNPCommutative, SDNPAssociative]
78 // out = min(a, b) a and b are floats
79 def AMDGPUfmin : SDNode<"AMDGPUISD::FMIN", SDTFPBinOp,
80 [SDNPCommutative, SDNPAssociative]
83 // out = min(a, b) a snd b are signed ints
84 def AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp,
85 [SDNPCommutative, SDNPAssociative]
88 // out = min(a, b) a and b are unsigned ints
89 def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
90 [SDNPCommutative, SDNPAssociative]
94 def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
96 def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
98 def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
100 def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
104 // urecip - This operation is a helper for integer division, it returns the
105 // result of 1 / a as a fractional unsigned integer.
106 // out = (2^32 / a) + e
107 // e is rounding error
108 def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
110 // Special case divide preop and flags.
111 def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
113 // Special case divide FMA with scale and flags (src0 = Quotient,
114 // src1 = Denominator, src2 = Numerator).
115 def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", SDTFPTernaryOp>;
117 // Single or double precision division fixup.
118 // Special case divide fixup and flags(src0 = Quotient, src1 =
119 // Denominator, src2 = Numerator).
120 def AMDGPUdiv_fixup : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
122 // Look Up 2.0 / pi src0 with segment select src1[4:0]
123 def AMDGPUtrig_preop : SDNode<"AMDGPUISD::TRIG_PREOP", AMDGPUTrigPreOp>;
125 def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
126 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
127 [SDNPHasChain, SDNPMayLoad]>;
129 def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
130 SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
131 [SDNPHasChain, SDNPMayStore]>;
133 // MSKOR instructions are atomic memory instructions used mainly for storing
134 // 8-bit and 16-bit values. The definition is:
136 // MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
138 // src0: vec4(src, 0, 0, mask)
139 // src1: dst - rat offset (aka pointer) in dwords
140 def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
141 SDTypeProfile<0, 2, []>,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
144 def AMDGPUround : SDNode<"ISD::FROUND",
145 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
147 def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
148 def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
149 def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
150 def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
152 def AMDGPUbrev : SDNode<"AMDGPUISD::BREV", SDTIntUnaryOp>;
154 // Signed and unsigned 24-bit mulitply. The highest 8-bits are ignore when
155 // performing the mulitply. The result is a 32-bit value.
156 def AMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
159 def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
163 def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
166 def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
170 //===----------------------------------------------------------------------===//
171 // Flow Control Profile Types
172 //===----------------------------------------------------------------------===//
173 // Branch instruction where second and third are basic blocks
174 def SDTIL_BRCond : SDTypeProfile<0, 2, [
178 //===----------------------------------------------------------------------===//
179 // Flow Control DAG Nodes
180 //===----------------------------------------------------------------------===//
181 def IL_brcond : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
183 //===----------------------------------------------------------------------===//
184 // Call/Return DAG Nodes
185 //===----------------------------------------------------------------------===//
186 def IL_retflag : SDNode<"AMDGPUISD::RET_FLAG", SDTNone,
187 [SDNPHasChain, SDNPOptInGlue]>;