1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Contains the definition of a TargetInstrInfo class that is common
14 //===----------------------------------------------------------------------===//
16 #ifndef AMDGPUINSTRUCTIONINFO_H
17 #define AMDGPUINSTRUCTIONINFO_H
19 #include "AMDGPUInstrInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "llvm/Target/TargetInstrInfo.h"
24 #define GET_INSTRINFO_HEADER
25 #define GET_INSTRINFO_ENUM
26 #include "AMDGPUGenInstrInfo.inc"
28 #define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT
29 #define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT
30 #define OPCODE_IS_ZERO AMDGPU::PRED_SETE
31 #define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE
35 class AMDGPUTargetMachine;
36 class MachineFunction;
38 class MachineInstrBuilder;
40 class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
42 const AMDGPURegisterInfo RI;
44 bool getNextBranchInstr(MachineBasicBlock::iterator &iter,
45 MachineBasicBlock &MBB) const;
47 explicit AMDGPUInstrInfo(TargetMachine &tm);
49 virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
51 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
52 unsigned &DstReg, unsigned &SubIdx) const;
54 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
55 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
56 int &FrameIndex) const;
57 bool hasLoadFromStackSlot(const MachineInstr *MI,
58 const MachineMemOperand *&MMO,
59 int &FrameIndex) const;
60 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
61 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
62 int &FrameIndex) const;
63 bool hasStoreFromStackSlot(const MachineInstr *MI,
64 const MachineMemOperand *&MMO,
65 int &FrameIndex) const;
68 convertToThreeAddress(MachineFunction::iterator &MFI,
69 MachineBasicBlock::iterator &MBBI,
70 LiveVariables *LV) const;
73 virtual void copyPhysReg(MachineBasicBlock &MBB,
74 MachineBasicBlock::iterator MI, DebugLoc DL,
75 unsigned DestReg, unsigned SrcReg,
76 bool KillSrc) const = 0;
78 void storeRegToStackSlot(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator MI,
80 unsigned SrcReg, bool isKill, int FrameIndex,
81 const TargetRegisterClass *RC,
82 const TargetRegisterInfo *TRI) const;
83 void loadRegFromStackSlot(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator MI,
85 unsigned DestReg, int FrameIndex,
86 const TargetRegisterClass *RC,
87 const TargetRegisterInfo *TRI) const;
90 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
92 const SmallVectorImpl<unsigned> &Ops,
93 int FrameIndex) const;
94 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
96 const SmallVectorImpl<unsigned> &Ops,
97 MachineInstr *LoadMI) const;
99 bool canFoldMemoryOperand(const MachineInstr *MI,
100 const SmallVectorImpl<unsigned> &Ops) const;
101 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
102 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
103 SmallVectorImpl<MachineInstr *> &NewMIs) const;
104 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
105 SmallVectorImpl<SDNode *> &NewNodes) const;
106 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
107 bool UnfoldLoad, bool UnfoldStore,
108 unsigned *LoadRegIndex = 0) const;
109 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
110 int64_t Offset1, int64_t Offset2,
111 unsigned NumLoads) const;
113 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
114 void insertNoop(MachineBasicBlock &MBB,
115 MachineBasicBlock::iterator MI) const;
116 bool isPredicated(const MachineInstr *MI) const;
117 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
118 const SmallVectorImpl<MachineOperand> &Pred2) const;
119 bool DefinesPredicate(MachineInstr *MI,
120 std::vector<MachineOperand> &Pred) const;
121 bool isPredicable(MachineInstr *MI) const;
122 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
124 // Helper functions that check the opcode for status information
125 bool isLoadInst(llvm::MachineInstr *MI) const;
126 bool isExtLoadInst(llvm::MachineInstr *MI) const;
127 bool isSWSExtLoadInst(llvm::MachineInstr *MI) const;
128 bool isSExtLoadInst(llvm::MachineInstr *MI) const;
129 bool isZExtLoadInst(llvm::MachineInstr *MI) const;
130 bool isAExtLoadInst(llvm::MachineInstr *MI) const;
131 bool isStoreInst(llvm::MachineInstr *MI) const;
132 bool isTruncStoreInst(llvm::MachineInstr *MI) const;
134 virtual MachineInstr* getMovImmInstr(MachineFunction *MF, unsigned DstReg,
135 int64_t Imm) const = 0;
136 virtual unsigned getIEQOpcode() const = 0;
137 virtual bool isMov(unsigned opcode) const = 0;
139 /// \brief Convert the AMDIL MachineInstr to a supported ISA
141 virtual void convertToISA(MachineInstr & MI, MachineFunction &MF,
146 } // End llvm namespace
148 #endif // AMDGPUINSTRINFO_H