1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPURegisterInfo.h"
19 #include "AMDGPUSubtarget.h"
20 #include "AMDILIntrinsicInfo.h"
21 #include "R600MachineFunctionInfo.h"
22 #include "SIMachineFunctionInfo.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/DataLayout.h"
32 #include "AMDGPUGenCallingConv.inc"
34 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
35 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
37 // Initialize target lowering borrowed from AMDIL
40 // We need to custom lower some of the intrinsics
41 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
43 // Library functions. These default to Expand, but we have instructions
45 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
46 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
47 setOperationAction(ISD::FPOW, MVT::f32, Legal);
48 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
49 setOperationAction(ISD::FABS, MVT::f32, Legal);
50 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
51 setOperationAction(ISD::FRINT, MVT::f32, Legal);
53 // The hardware supports ROTR, but not ROTL
54 setOperationAction(ISD::ROTL, MVT::i32, Expand);
56 // Lower floating point store/load to integer store/load to reduce the number
57 // of patterns in tablegen.
58 setOperationAction(ISD::STORE, MVT::f32, Promote);
59 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
61 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
62 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
64 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
65 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
67 setOperationAction(ISD::STORE, MVT::f64, Promote);
68 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
70 // Custom lowering of vector stores is required for local address space
72 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
73 // XXX: Native v2i32 local address space stores are possible, but not
74 // currently implemented.
75 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
77 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
78 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
79 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
80 // XXX: This can be change to Custom, once ExpandVectorStores can
81 // handle 64-bit stores.
82 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
84 setOperationAction(ISD::LOAD, MVT::f32, Promote);
85 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
87 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
88 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
90 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
91 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
93 setOperationAction(ISD::LOAD, MVT::f64, Promote);
94 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
96 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
97 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
98 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
99 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
101 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
102 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
103 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
104 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
105 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
106 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
107 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
108 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
109 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
110 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
111 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
112 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
114 setOperationAction(ISD::FNEG, MVT::v2f32, Expand);
115 setOperationAction(ISD::FNEG, MVT::v4f32, Expand);
117 setOperationAction(ISD::MUL, MVT::i64, Expand);
119 setOperationAction(ISD::UDIV, MVT::i32, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
121 setOperationAction(ISD::UREM, MVT::i32, Expand);
122 setOperationAction(ISD::VSELECT, MVT::v2f32, Expand);
123 setOperationAction(ISD::VSELECT, MVT::v4f32, Expand);
125 static const MVT::SimpleValueType IntTypes[] = {
126 MVT::v2i32, MVT::v4i32
128 const size_t NumIntTypes = array_lengthof(IntTypes);
130 for (unsigned int x = 0; x < NumIntTypes; ++x) {
131 MVT::SimpleValueType VT = IntTypes[x];
132 //Expand the following operations for the current type by default
133 setOperationAction(ISD::ADD, VT, Expand);
134 setOperationAction(ISD::AND, VT, Expand);
135 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
136 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
137 setOperationAction(ISD::MUL, VT, Expand);
138 setOperationAction(ISD::OR, VT, Expand);
139 setOperationAction(ISD::SHL, VT, Expand);
140 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
141 setOperationAction(ISD::SRL, VT, Expand);
142 setOperationAction(ISD::SRA, VT, Expand);
143 setOperationAction(ISD::SUB, VT, Expand);
144 setOperationAction(ISD::UDIV, VT, Expand);
145 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
146 setOperationAction(ISD::UREM, VT, Expand);
147 setOperationAction(ISD::VSELECT, VT, Expand);
148 setOperationAction(ISD::XOR, VT, Expand);
151 static const MVT::SimpleValueType FloatTypes[] = {
152 MVT::v2f32, MVT::v4f32
154 const size_t NumFloatTypes = array_lengthof(FloatTypes);
156 for (unsigned int x = 0; x < NumFloatTypes; ++x) {
157 MVT::SimpleValueType VT = FloatTypes[x];
158 setOperationAction(ISD::FADD, VT, Expand);
159 setOperationAction(ISD::FDIV, VT, Expand);
160 setOperationAction(ISD::FFLOOR, VT, Expand);
161 setOperationAction(ISD::FMUL, VT, Expand);
162 setOperationAction(ISD::FRINT, VT, Expand);
163 setOperationAction(ISD::FSUB, VT, Expand);
167 //===----------------------------------------------------------------------===//
168 // Target Information
169 //===----------------------------------------------------------------------===//
171 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
176 //===---------------------------------------------------------------------===//
178 //===---------------------------------------------------------------------===//
180 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
181 assert(VT.isFloatingPoint());
182 return VT == MVT::f32;
185 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
186 assert(VT.isFloatingPoint());
187 return VT == MVT::f32;
190 //===---------------------------------------------------------------------===//
191 // TargetLowering Callbacks
192 //===---------------------------------------------------------------------===//
194 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
195 const SmallVectorImpl<ISD::InputArg> &Ins) const {
197 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
200 SDValue AMDGPUTargetLowering::LowerReturn(
202 CallingConv::ID CallConv,
204 const SmallVectorImpl<ISD::OutputArg> &Outs,
205 const SmallVectorImpl<SDValue> &OutVals,
206 SDLoc DL, SelectionDAG &DAG) const {
207 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
210 //===---------------------------------------------------------------------===//
211 // Target specific lowering
212 //===---------------------------------------------------------------------===//
214 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
216 switch (Op.getOpcode()) {
218 Op.getNode()->dump();
219 assert(0 && "Custom lowering code for this"
220 "instruction is not implemented yet!");
222 // AMDIL DAG lowering
223 case ISD::SDIV: return LowerSDIV(Op, DAG);
224 case ISD::SREM: return LowerSREM(Op, DAG);
225 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
226 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
227 // AMDGPU DAG lowering
228 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
229 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
230 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
231 case ISD::STORE: return LowerSTORE(Op, DAG);
232 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
237 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
239 SelectionDAG &DAG) const {
241 const DataLayout *TD = getTargetMachine().getDataLayout();
242 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
244 assert(G->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS);
245 // XXX: What does the value of G->getOffset() mean?
246 assert(G->getOffset() == 0 &&
247 "Do not know what to do with an non-zero offset");
249 unsigned Offset = MFI->LDSSize;
250 const GlobalValue *GV = G->getGlobal();
251 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
253 // XXX: Account for alignment?
254 MFI->LDSSize += Size;
256 return DAG.getConstant(Offset, getPointerTy(G->getAddressSpace()));
259 void AMDGPUTargetLowering::ExtractVectorElements(SDValue Op, SelectionDAG &DAG,
260 SmallVectorImpl<SDValue> &Args,
262 unsigned Count) const {
263 EVT VT = Op.getValueType();
264 for (unsigned i = Start, e = Start + Count; i != e; ++i) {
265 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
266 VT.getVectorElementType(),
267 Op, DAG.getConstant(i, MVT::i32)));
271 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
272 SelectionDAG &DAG) const {
273 SmallVector<SDValue, 8> Args;
274 SDValue A = Op.getOperand(0);
275 SDValue B = Op.getOperand(1);
277 ExtractVectorElements(A, DAG, Args, 0,
278 A.getValueType().getVectorNumElements());
279 ExtractVectorElements(B, DAG, Args, 0,
280 B.getValueType().getVectorNumElements());
282 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(),
283 &Args[0], Args.size());
286 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
287 SelectionDAG &DAG) const {
289 SmallVector<SDValue, 8> Args;
290 EVT VT = Op.getValueType();
291 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
292 ExtractVectorElements(Op.getOperand(0), DAG, Args, Start,
293 VT.getVectorNumElements());
295 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(),
296 &Args[0], Args.size());
300 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
301 SelectionDAG &DAG) const {
302 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
304 EVT VT = Op.getValueType();
306 switch (IntrinsicID) {
308 case AMDGPUIntrinsic::AMDIL_abs:
309 return LowerIntrinsicIABS(Op, DAG);
310 case AMDGPUIntrinsic::AMDIL_exp:
311 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
312 case AMDGPUIntrinsic::AMDGPU_lrp:
313 return LowerIntrinsicLRP(Op, DAG);
314 case AMDGPUIntrinsic::AMDIL_fraction:
315 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
316 case AMDGPUIntrinsic::AMDIL_max:
317 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
319 case AMDGPUIntrinsic::AMDGPU_imax:
320 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
322 case AMDGPUIntrinsic::AMDGPU_umax:
323 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
325 case AMDGPUIntrinsic::AMDIL_min:
326 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
328 case AMDGPUIntrinsic::AMDGPU_imin:
329 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
331 case AMDGPUIntrinsic::AMDGPU_umin:
332 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
334 case AMDGPUIntrinsic::AMDIL_round_nearest:
335 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
339 ///IABS(a) = SMAX(sub(0, a), a)
340 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
341 SelectionDAG &DAG) const {
344 EVT VT = Op.getValueType();
345 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
348 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
351 /// Linear Interpolation
352 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
353 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
354 SelectionDAG &DAG) const {
356 EVT VT = Op.getValueType();
357 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
358 DAG.getConstantFP(1.0f, MVT::f32),
360 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
362 return DAG.getNode(ISD::FADD, DL, VT,
363 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
367 /// \brief Generate Min/Max node
368 SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op,
369 SelectionDAG &DAG) const {
371 EVT VT = Op.getValueType();
373 SDValue LHS = Op.getOperand(0);
374 SDValue RHS = Op.getOperand(1);
375 SDValue True = Op.getOperand(2);
376 SDValue False = Op.getOperand(3);
377 SDValue CC = Op.getOperand(4);
379 if (VT != MVT::f32 ||
380 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
384 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
398 assert(0 && "Operation should already be optimised !");
406 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
408 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
417 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
419 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
421 case ISD::SETCC_INVALID:
422 assert(0 && "Invalid setcc condcode !");
427 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
428 SelectionDAG &DAG) const {
429 StoreSDNode *Store = dyn_cast<StoreSDNode>(Op);
430 EVT MemVT = Store->getMemoryVT();
431 unsigned MemBits = MemVT.getSizeInBits();
433 // Byte stores are really expensive, so if possible, try to pack
434 // 32-bit vector truncatating store into an i32 store.
435 // XXX: We could also handle optimize other vector bitwidths
436 if (!MemVT.isVector() || MemBits > 32) {
441 const SDValue &Value = Store->getValue();
442 EVT VT = Value.getValueType();
443 const SDValue &Ptr = Store->getBasePtr();
444 EVT MemEltVT = MemVT.getVectorElementType();
445 unsigned MemEltBits = MemEltVT.getSizeInBits();
446 unsigned MemNumElements = MemVT.getVectorNumElements();
447 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits());
451 Mask = DAG.getConstant(0xFF, PackedVT);
454 Mask = DAG.getConstant(0xFFFF, PackedVT);
457 llvm_unreachable("Cannot lower this vector store");
460 for (unsigned i = 0; i < MemNumElements; ++i) {
461 EVT ElemVT = VT.getVectorElementType();
462 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
463 DAG.getConstant(i, MVT::i32));
464 Elt = DAG.getZExtOrTrunc(Elt, DL, PackedVT);
465 Elt = DAG.getNode(ISD::AND, DL, PackedVT, Elt, Mask);
466 SDValue Shift = DAG.getConstant(MemEltBits * i, PackedVT);
467 Elt = DAG.getNode(ISD::SHL, DL, PackedVT, Elt, Shift);
471 PackedValue = DAG.getNode(ISD::OR, DL, PackedVT, PackedValue, Elt);
474 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
475 MachinePointerInfo(Store->getMemOperand()->getValue()),
476 Store->isVolatile(), Store->isNonTemporal(),
477 Store->getAlignment());
480 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
481 SelectionDAG &DAG) const {
482 StoreSDNode *Store = cast<StoreSDNode>(Op);
483 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
484 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
485 EVT PtrVT = Store->getBasePtr().getValueType();
486 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
489 SmallVector<SDValue, 8> Chains;
491 for (unsigned i = 0, e = NumElts; i != e; ++i) {
492 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
493 Store->getValue(), DAG.getConstant(i, MVT::i32));
494 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT,
496 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8),
498 Chains.push_back(DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
499 MachinePointerInfo(Store->getMemOperand()->getValue()),
500 MemEltVT, Store->isVolatile(), Store->isNonTemporal(),
501 Store->getAlignment()));
503 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, &Chains[0], NumElts);
506 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
507 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
508 if (Result.getNode()) {
512 StoreSDNode *Store = cast<StoreSDNode>(Op);
513 if (Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
514 Store->getValue().getValueType().isVector()) {
515 return SplitVectorStore(Op, DAG);
520 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
521 SelectionDAG &DAG) const {
523 EVT VT = Op.getValueType();
525 SDValue Num = Op.getOperand(0);
526 SDValue Den = Op.getOperand(1);
528 SmallVector<SDValue, 8> Results;
530 // RCP = URECIP(Den) = 2^32 / Den + e
531 // e is rounding error.
532 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
534 // RCP_LO = umulo(RCP, Den) */
535 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
537 // RCP_HI = mulhu (RCP, Den) */
538 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
540 // NEG_RCP_LO = -RCP_LO
541 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
544 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
545 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
548 // Calculate the rounding error from the URECIP instruction
549 // E = mulhu(ABS_RCP_LO, RCP)
550 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
553 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
556 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
558 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
559 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
562 // Quotient = mulhu(Tmp0, Num)
563 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
565 // Num_S_Remainder = Quotient * Den
566 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
568 // Remainder = Num - Num_S_Remainder
569 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
571 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
572 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
573 DAG.getConstant(-1, VT),
574 DAG.getConstant(0, VT),
576 // Remainder_GE_Zero = (Remainder >= 0 ? -1 : 0)
577 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Remainder,
578 DAG.getConstant(0, VT),
579 DAG.getConstant(-1, VT),
580 DAG.getConstant(0, VT),
582 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
583 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
586 // Calculate Division result:
588 // Quotient_A_One = Quotient + 1
589 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
590 DAG.getConstant(1, VT));
592 // Quotient_S_One = Quotient - 1
593 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
594 DAG.getConstant(1, VT));
596 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
597 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
598 Quotient, Quotient_A_One, ISD::SETEQ);
600 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
601 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
602 Quotient_S_One, Div, ISD::SETEQ);
604 // Calculate Rem result:
606 // Remainder_S_Den = Remainder - Den
607 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
609 // Remainder_A_Den = Remainder + Den
610 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
612 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
613 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
614 Remainder, Remainder_S_Den, ISD::SETEQ);
616 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
617 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
618 Remainder_A_Den, Rem, ISD::SETEQ);
622 return DAG.getMergeValues(Ops, 2, DL);
626 //===----------------------------------------------------------------------===//
628 //===----------------------------------------------------------------------===//
630 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
631 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
632 return CFP->isExactlyValue(1.0);
634 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
635 return C->isAllOnesValue();
640 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
641 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
642 return CFP->getValueAPF().isZero();
644 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
645 return C->isNullValue();
650 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
651 const TargetRegisterClass *RC,
652 unsigned Reg, EVT VT) const {
653 MachineFunction &MF = DAG.getMachineFunction();
654 MachineRegisterInfo &MRI = MF.getRegInfo();
655 unsigned VirtualRegister;
656 if (!MRI.isLiveIn(Reg)) {
657 VirtualRegister = MRI.createVirtualRegister(RC);
658 MRI.addLiveIn(Reg, VirtualRegister);
660 VirtualRegister = MRI.getLiveInVirtReg(Reg);
662 return DAG.getRegister(VirtualRegister, VT);
665 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
667 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
671 NODE_NAME_CASE(CALL);
672 NODE_NAME_CASE(UMUL);
673 NODE_NAME_CASE(DIV_INF);
674 NODE_NAME_CASE(RET_FLAG);
675 NODE_NAME_CASE(BRANCH_COND);
678 NODE_NAME_CASE(DWORDADDR)
679 NODE_NAME_CASE(FRACT)
686 NODE_NAME_CASE(URECIP)
687 NODE_NAME_CASE(EXPORT)
688 NODE_NAME_CASE(CONST_ADDRESS)
689 NODE_NAME_CASE(REGISTER_LOAD)
690 NODE_NAME_CASE(REGISTER_STORE)
691 NODE_NAME_CASE(LOAD_CONSTANT)
692 NODE_NAME_CASE(LOAD_INPUT)
693 NODE_NAME_CASE(SAMPLE)
694 NODE_NAME_CASE(SAMPLEB)
695 NODE_NAME_CASE(SAMPLED)
696 NODE_NAME_CASE(SAMPLEL)
697 NODE_NAME_CASE(STORE_MSKOR)