1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DiagnosticInfo.h"
32 #include "llvm/IR/DiagnosticPrinter.h"
38 /// Diagnostic information for unimplemented or unsupported feature reporting.
39 class DiagnosticInfoUnsupported : public DiagnosticInfo {
41 const Twine &Description;
46 static int getKindID() {
48 KindID = llvm::getNextAvailablePluginDiagnosticKind();
53 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
54 DiagnosticSeverity Severity = DS_Error)
55 : DiagnosticInfo(getKindID(), Severity),
59 const Function &getFunction() const { return Fn; }
60 const Twine &getDescription() const { return Description; }
62 void print(DiagnosticPrinter &DP) const override {
63 DP << "unsupported " << getDescription() << " in " << Fn.getName();
66 static bool classof(const DiagnosticInfo *DI) {
67 return DI->getKind() == getKindID();
71 int DiagnosticInfoUnsupported::KindID = 0;
75 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
76 CCValAssign::LocInfo LocInfo,
77 ISD::ArgFlagsTy ArgFlags, CCState &State) {
78 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
79 ArgFlags.getOrigAlign());
80 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
85 #include "AMDGPUGenCallingConv.inc"
87 // Find a larger type to do a load / store of a vector with.
88 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
89 unsigned StoreSize = VT.getStoreSizeInBits();
91 return EVT::getIntegerVT(Ctx, StoreSize);
93 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
94 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
97 // Type for a vector that will be loaded to.
98 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
99 unsigned StoreSize = VT.getStoreSizeInBits();
101 return EVT::getIntegerVT(Ctx, 32);
103 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
106 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
107 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
109 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
111 setOperationAction(ISD::Constant, MVT::i32, Legal);
112 setOperationAction(ISD::Constant, MVT::i64, Legal);
113 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
114 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
116 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
117 setOperationAction(ISD::BRIND, MVT::Other, Expand);
119 // We need to custom lower some of the intrinsics
120 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
122 // Library functions. These default to Expand, but we have instructions
124 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
125 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
126 setOperationAction(ISD::FPOW, MVT::f32, Legal);
127 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
128 setOperationAction(ISD::FABS, MVT::f32, Legal);
129 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
130 setOperationAction(ISD::FRINT, MVT::f32, Legal);
131 setOperationAction(ISD::FROUND, MVT::f32, Legal);
132 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
134 // Lower floating point store/load to integer store/load to reduce the number
135 // of patterns in tablegen.
136 setOperationAction(ISD::STORE, MVT::f32, Promote);
137 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
139 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
140 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
142 setOperationAction(ISD::STORE, MVT::i64, Promote);
143 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
145 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
146 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
148 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
149 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
151 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
152 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
154 setOperationAction(ISD::STORE, MVT::f64, Promote);
155 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
157 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
158 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
160 // Custom lowering of vector stores is required for local address space
162 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
163 // XXX: Native v2i32 local address space stores are possible, but not
164 // currently implemented.
165 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
167 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
168 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
169 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
171 // XXX: This can be change to Custom, once ExpandVectorStores can
172 // handle 64-bit stores.
173 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
175 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
176 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
177 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
178 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
179 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
182 setOperationAction(ISD::LOAD, MVT::f32, Promote);
183 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
185 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
186 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
188 setOperationAction(ISD::LOAD, MVT::i64, Promote);
189 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
191 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
192 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
194 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
195 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
197 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
198 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
200 setOperationAction(ISD::LOAD, MVT::f64, Promote);
201 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
203 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
204 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
206 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
207 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
208 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
209 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
210 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
211 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
213 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
214 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
215 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
217 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
218 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
219 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
220 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
221 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
222 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
223 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
224 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
225 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
226 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
227 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
228 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
230 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
232 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
233 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
234 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
235 setOperationAction(ISD::FRINT, MVT::f64, Custom);
236 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
239 if (!Subtarget->hasBFI()) {
240 // fcopysign can be done in a single instruction with BFI.
241 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
242 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
245 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
246 for (MVT VT : ScalarIntVTs) {
247 setOperationAction(ISD::SREM, VT, Expand);
248 setOperationAction(ISD::SDIV, VT, Expand);
250 // GPU does not have divrem function for signed or unsigned.
251 setOperationAction(ISD::SDIVREM, VT, Custom);
252 setOperationAction(ISD::UDIVREM, VT, Custom);
254 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
255 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
256 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
258 setOperationAction(ISD::BSWAP, VT, Expand);
259 setOperationAction(ISD::CTTZ, VT, Expand);
260 setOperationAction(ISD::CTLZ, VT, Expand);
263 if (!Subtarget->hasBCNT(32))
264 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
266 if (!Subtarget->hasBCNT(64))
267 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
269 // The hardware supports 32-bit ROTR, but not ROTL.
270 setOperationAction(ISD::ROTL, MVT::i32, Expand);
271 setOperationAction(ISD::ROTL, MVT::i64, Expand);
272 setOperationAction(ISD::ROTR, MVT::i64, Expand);
274 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
275 setOperationAction(ISD::MUL, MVT::i64, Expand);
276 setOperationAction(ISD::MULHU, MVT::i64, Expand);
277 setOperationAction(ISD::MULHS, MVT::i64, Expand);
278 setOperationAction(ISD::UDIV, MVT::i32, Expand);
279 setOperationAction(ISD::UREM, MVT::i32, Expand);
280 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
281 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
283 static const MVT::SimpleValueType VectorIntTypes[] = {
284 MVT::v2i32, MVT::v4i32
287 for (MVT VT : VectorIntTypes) {
288 // Expand the following operations for the current type by default.
289 setOperationAction(ISD::ADD, VT, Expand);
290 setOperationAction(ISD::AND, VT, Expand);
291 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
292 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
293 setOperationAction(ISD::MUL, VT, Expand);
294 setOperationAction(ISD::OR, VT, Expand);
295 setOperationAction(ISD::SHL, VT, Expand);
296 setOperationAction(ISD::SRA, VT, Expand);
297 setOperationAction(ISD::SRL, VT, Expand);
298 setOperationAction(ISD::ROTL, VT, Expand);
299 setOperationAction(ISD::ROTR, VT, Expand);
300 setOperationAction(ISD::SUB, VT, Expand);
301 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
302 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
303 // TODO: Implement custom UREM / SREM routines.
304 setOperationAction(ISD::SDIV, VT, Expand);
305 setOperationAction(ISD::UDIV, VT, Expand);
306 setOperationAction(ISD::SREM, VT, Expand);
307 setOperationAction(ISD::UREM, VT, Expand);
308 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
309 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
310 setOperationAction(ISD::SDIVREM, VT, Custom);
311 setOperationAction(ISD::UDIVREM, VT, Custom);
312 setOperationAction(ISD::ADDC, VT, Expand);
313 setOperationAction(ISD::SUBC, VT, Expand);
314 setOperationAction(ISD::ADDE, VT, Expand);
315 setOperationAction(ISD::SUBE, VT, Expand);
316 setOperationAction(ISD::SELECT, VT, Expand);
317 setOperationAction(ISD::VSELECT, VT, Expand);
318 setOperationAction(ISD::SELECT_CC, VT, Expand);
319 setOperationAction(ISD::XOR, VT, Expand);
320 setOperationAction(ISD::BSWAP, VT, Expand);
321 setOperationAction(ISD::CTPOP, VT, Expand);
322 setOperationAction(ISD::CTTZ, VT, Expand);
323 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
324 setOperationAction(ISD::CTLZ, VT, Expand);
325 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
326 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
329 static const MVT::SimpleValueType FloatVectorTypes[] = {
330 MVT::v2f32, MVT::v4f32
333 for (MVT VT : FloatVectorTypes) {
334 setOperationAction(ISD::FABS, VT, Expand);
335 setOperationAction(ISD::FADD, VT, Expand);
336 setOperationAction(ISD::FCEIL, VT, Expand);
337 setOperationAction(ISD::FCOS, VT, Expand);
338 setOperationAction(ISD::FDIV, VT, Expand);
339 setOperationAction(ISD::FEXP2, VT, Expand);
340 setOperationAction(ISD::FLOG2, VT, Expand);
341 setOperationAction(ISD::FPOW, VT, Expand);
342 setOperationAction(ISD::FFLOOR, VT, Expand);
343 setOperationAction(ISD::FTRUNC, VT, Expand);
344 setOperationAction(ISD::FMUL, VT, Expand);
345 setOperationAction(ISD::FMA, VT, Expand);
346 setOperationAction(ISD::FRINT, VT, Expand);
347 setOperationAction(ISD::FNEARBYINT, VT, Expand);
348 setOperationAction(ISD::FSQRT, VT, Expand);
349 setOperationAction(ISD::FSIN, VT, Expand);
350 setOperationAction(ISD::FSUB, VT, Expand);
351 setOperationAction(ISD::FNEG, VT, Expand);
352 setOperationAction(ISD::SELECT, VT, Expand);
353 setOperationAction(ISD::VSELECT, VT, Expand);
354 setOperationAction(ISD::SELECT_CC, VT, Expand);
355 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
356 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
359 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
360 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
362 setTargetDAGCombine(ISD::MUL);
363 setTargetDAGCombine(ISD::SELECT_CC);
365 setSchedulingPreference(Sched::RegPressure);
366 setJumpIsExpensive(true);
368 setSelectIsExpensive(false);
369 PredictableSelectIsExpensive = false;
371 // There are no integer divide instructions, and these expand to a pretty
372 // large sequence of instructions.
373 setIntDivIsCheap(false);
374 setPow2DivIsCheap(false);
376 // TODO: Investigate this when 64-bit divides are implemented.
377 addBypassSlowDiv(64, 32);
379 // FIXME: Need to really handle these.
380 MaxStoresPerMemcpy = 4096;
381 MaxStoresPerMemmove = 4096;
382 MaxStoresPerMemset = 4096;
385 //===----------------------------------------------------------------------===//
386 // Target Information
387 //===----------------------------------------------------------------------===//
389 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
393 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
397 // The backend supports 32 and 64 bit floating point immediates.
398 // FIXME: Why are we reporting vectors of FP immediates as legal?
399 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
400 EVT ScalarVT = VT.getScalarType();
401 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
404 // We don't want to shrink f64 / f32 constants.
405 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
406 EVT ScalarVT = VT.getScalarType();
407 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
410 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
412 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
415 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
416 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
418 return ((LScalarSize <= CastScalarSize) ||
419 (CastScalarSize >= 32) ||
423 //===---------------------------------------------------------------------===//
425 //===---------------------------------------------------------------------===//
427 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
428 assert(VT.isFloatingPoint());
429 return VT == MVT::f32;
432 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
433 assert(VT.isFloatingPoint());
434 return VT == MVT::f32;
437 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
438 // Truncate is just accessing a subregister.
439 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
442 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
443 // Truncate is just accessing a subregister.
444 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
445 (Dest->getPrimitiveSizeInBits() % 32 == 0);
448 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
449 const DataLayout *DL = getDataLayout();
450 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
451 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
453 return SrcSize == 32 && DestSize == 64;
456 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
457 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
458 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
459 // this will enable reducing 64-bit operations the 32-bit, which is always
461 return Src == MVT::i32 && Dest == MVT::i64;
464 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
465 return isZExtFree(Val.getValueType(), VT2);
468 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
469 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
470 // limited number of native 64-bit operations. Shrinking an operation to fit
471 // in a single 32-bit register should always be helpful. As currently used,
472 // this is much less general than the name suggests, and is only used in
473 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
474 // not profitable, and may actually be harmful.
475 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
478 //===---------------------------------------------------------------------===//
479 // TargetLowering Callbacks
480 //===---------------------------------------------------------------------===//
482 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
483 const SmallVectorImpl<ISD::InputArg> &Ins) const {
485 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
488 SDValue AMDGPUTargetLowering::LowerReturn(
490 CallingConv::ID CallConv,
492 const SmallVectorImpl<ISD::OutputArg> &Outs,
493 const SmallVectorImpl<SDValue> &OutVals,
494 SDLoc DL, SelectionDAG &DAG) const {
495 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
498 //===---------------------------------------------------------------------===//
499 // Target specific lowering
500 //===---------------------------------------------------------------------===//
502 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
503 SmallVectorImpl<SDValue> &InVals) const {
504 SDValue Callee = CLI.Callee;
505 SelectionDAG &DAG = CLI.DAG;
507 const Function &Fn = *DAG.getMachineFunction().getFunction();
509 StringRef FuncName("<unknown>");
511 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
512 FuncName = G->getSymbol();
513 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
514 FuncName = G->getGlobal()->getName();
516 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
517 DAG.getContext()->diagnose(NoCalls);
521 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
522 SelectionDAG &DAG) const {
523 switch (Op.getOpcode()) {
525 Op.getNode()->dump();
526 llvm_unreachable("Custom lowering code for this"
527 "instruction is not implemented yet!");
529 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
530 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
531 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
532 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
533 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
534 case ISD::SDIV: return LowerSDIV(Op, DAG);
535 case ISD::SREM: return LowerSREM(Op, DAG);
536 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
537 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
538 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
539 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
540 case ISD::FRINT: return LowerFRINT(Op, DAG);
541 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
542 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
543 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
548 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
549 SmallVectorImpl<SDValue> &Results,
550 SelectionDAG &DAG) const {
551 switch (N->getOpcode()) {
552 case ISD::SIGN_EXTEND_INREG:
553 // Different parts of legalization seem to interpret which type of
554 // sign_extend_inreg is the one to check for custom lowering. The extended
555 // from type is what really matters, but some places check for custom
556 // lowering of the result type. This results in trying to use
557 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
558 // nothing here and let the illegal result integer be handled normally.
561 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
565 Results.push_back(SDValue(Node, 0));
566 Results.push_back(SDValue(Node, 1));
567 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
569 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
573 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
574 if (Lowered.getNode())
575 Results.push_back(Lowered);
583 // FIXME: This implements accesses to initialized globals in the constant
584 // address space by copying them to private and accessing that. It does not
585 // properly handle illegal types or vectors. The private vector loads are not
586 // scalarized, and the illegal scalars hit an assertion. This technique will not
587 // work well with large initializers, and this should eventually be
588 // removed. Initialized globals should be placed into a data section that the
589 // runtime will load into a buffer before the kernel is executed. Uses of the
590 // global need to be replaced with a pointer loaded from an implicit kernel
591 // argument into this buffer holding the copy of the data, which will remove the
592 // need for any of this.
593 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
594 const GlobalValue *GV,
595 const SDValue &InitPtr,
597 SelectionDAG &DAG) const {
598 const DataLayout *TD = getTargetMachine().getDataLayout();
600 Type *InitTy = Init->getType();
602 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
603 EVT VT = EVT::getEVT(InitTy);
604 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
605 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
606 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
607 TD->getPrefTypeAlignment(InitTy));
610 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
611 EVT VT = EVT::getEVT(CFP->getType());
612 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
613 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
614 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
615 TD->getPrefTypeAlignment(CFP->getType()));
618 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
619 const StructLayout *SL = TD->getStructLayout(ST);
621 EVT PtrVT = InitPtr.getValueType();
622 SmallVector<SDValue, 8> Chains;
624 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
625 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
626 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
628 Constant *Elt = Init->getAggregateElement(I);
629 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
632 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
635 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
636 EVT PtrVT = InitPtr.getValueType();
638 unsigned NumElements;
639 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
640 NumElements = AT->getNumElements();
641 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
642 NumElements = VT->getNumElements();
644 llvm_unreachable("Unexpected type");
646 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
647 SmallVector<SDValue, 8> Chains;
648 for (unsigned i = 0; i < NumElements; ++i) {
649 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
650 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
652 Constant *Elt = Init->getAggregateElement(i);
653 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
656 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
659 if (isa<UndefValue>(Init)) {
660 EVT VT = EVT::getEVT(InitTy);
661 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
662 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
663 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
664 TD->getPrefTypeAlignment(InitTy));
668 llvm_unreachable("Unhandled constant initializer");
671 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
673 SelectionDAG &DAG) const {
675 const DataLayout *TD = getTargetMachine().getDataLayout();
676 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
677 const GlobalValue *GV = G->getGlobal();
679 switch (G->getAddressSpace()) {
680 default: llvm_unreachable("Global Address lowering not implemented for this "
682 case AMDGPUAS::LOCAL_ADDRESS: {
683 // XXX: What does the value of G->getOffset() mean?
684 assert(G->getOffset() == 0 &&
685 "Do not know what to do with an non-zero offset");
688 if (MFI->LocalMemoryObjects.count(GV) == 0) {
689 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
690 Offset = MFI->LDSSize;
691 MFI->LocalMemoryObjects[GV] = Offset;
692 // XXX: Account for alignment?
693 MFI->LDSSize += Size;
695 Offset = MFI->LocalMemoryObjects[GV];
698 return DAG.getConstant(Offset, getPointerTy(G->getAddressSpace()));
700 case AMDGPUAS::CONSTANT_ADDRESS: {
701 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
702 Type *EltType = GV->getType()->getElementType();
703 unsigned Size = TD->getTypeAllocSize(EltType);
704 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
706 MVT PrivPtrVT = getPointerTy(AMDGPUAS::PRIVATE_ADDRESS);
707 MVT ConstPtrVT = getPointerTy(AMDGPUAS::CONSTANT_ADDRESS);
709 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
710 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
712 const GlobalVariable *Var = cast<GlobalVariable>(GV);
713 if (!Var->hasInitializer()) {
714 // This has no use, but bugpoint will hit it.
715 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
718 const Constant *Init = Var->getInitializer();
719 SmallVector<SDNode*, 8> WorkList;
721 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
722 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
723 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
725 WorkList.push_back(*I);
727 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
728 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
729 E = WorkList.end(); I != E; ++I) {
730 SmallVector<SDValue, 8> Ops;
731 Ops.push_back(Chain);
732 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
733 Ops.push_back((*I)->getOperand(i));
735 DAG.UpdateNodeOperands(*I, Ops);
737 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
742 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
743 SelectionDAG &DAG) const {
744 SmallVector<SDValue, 8> Args;
745 SDValue A = Op.getOperand(0);
746 SDValue B = Op.getOperand(1);
748 DAG.ExtractVectorElements(A, Args);
749 DAG.ExtractVectorElements(B, Args);
751 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
754 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
755 SelectionDAG &DAG) const {
757 SmallVector<SDValue, 8> Args;
758 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
759 EVT VT = Op.getValueType();
760 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
761 VT.getVectorNumElements());
763 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
766 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
767 SelectionDAG &DAG) const {
769 MachineFunction &MF = DAG.getMachineFunction();
770 const AMDGPUFrameLowering *TFL =
771 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
773 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
775 unsigned FrameIndex = FIN->getIndex();
776 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
777 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
781 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
782 SelectionDAG &DAG) const {
783 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
785 EVT VT = Op.getValueType();
787 switch (IntrinsicID) {
789 case AMDGPUIntrinsic::AMDGPU_abs:
790 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
791 return LowerIntrinsicIABS(Op, DAG);
792 case AMDGPUIntrinsic::AMDGPU_lrp:
793 return LowerIntrinsicLRP(Op, DAG);
794 case AMDGPUIntrinsic::AMDGPU_fract:
795 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
796 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
798 case AMDGPUIntrinsic::AMDGPU_clamp:
799 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
800 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
801 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
803 case Intrinsic::AMDGPU_div_scale: {
804 // 3rd parameter required to be a constant.
805 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
807 return DAG.getUNDEF(VT);
809 // Translate to the operands expected by the machine instruction. The
810 // first parameter must be the same as the first instruction.
811 SDValue Numerator = Op.getOperand(1);
812 SDValue Denominator = Op.getOperand(2);
813 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
815 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, VT,
816 Src0, Denominator, Numerator);
819 case Intrinsic::AMDGPU_div_fmas:
820 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
821 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
823 case Intrinsic::AMDGPU_div_fixup:
824 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
825 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
827 case Intrinsic::AMDGPU_trig_preop:
828 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
829 Op.getOperand(1), Op.getOperand(2));
831 case Intrinsic::AMDGPU_rcp:
832 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
834 case Intrinsic::AMDGPU_rsq:
835 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
837 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
838 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
840 case Intrinsic::AMDGPU_rsq_clamped:
841 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
843 case AMDGPUIntrinsic::AMDGPU_imax:
844 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
846 case AMDGPUIntrinsic::AMDGPU_umax:
847 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
849 case AMDGPUIntrinsic::AMDGPU_imin:
850 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
852 case AMDGPUIntrinsic::AMDGPU_umin:
853 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
856 case AMDGPUIntrinsic::AMDGPU_umul24:
857 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
858 Op.getOperand(1), Op.getOperand(2));
860 case AMDGPUIntrinsic::AMDGPU_imul24:
861 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
862 Op.getOperand(1), Op.getOperand(2));
864 case AMDGPUIntrinsic::AMDGPU_umad24:
865 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
866 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
868 case AMDGPUIntrinsic::AMDGPU_imad24:
869 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
870 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
872 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
873 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
875 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
876 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
878 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
879 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
881 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
882 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
884 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
885 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
890 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
891 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
896 case AMDGPUIntrinsic::AMDGPU_bfi:
897 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
902 case AMDGPUIntrinsic::AMDGPU_bfm:
903 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
907 case AMDGPUIntrinsic::AMDGPU_brev:
908 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
910 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
911 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
913 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
914 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
915 case AMDGPUIntrinsic::AMDGPU_trunc:
916 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
920 ///IABS(a) = SMAX(sub(0, a), a)
921 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
922 SelectionDAG &DAG) const {
924 EVT VT = Op.getValueType();
925 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
928 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
931 /// Linear Interpolation
932 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
933 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
934 SelectionDAG &DAG) const {
936 EVT VT = Op.getValueType();
937 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
938 DAG.getConstantFP(1.0f, MVT::f32),
940 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
942 return DAG.getNode(ISD::FADD, DL, VT,
943 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
947 /// \brief Generate Min/Max node
948 SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N,
949 SelectionDAG &DAG) const {
951 EVT VT = N->getValueType(0);
953 SDValue LHS = N->getOperand(0);
954 SDValue RHS = N->getOperand(1);
955 SDValue True = N->getOperand(2);
956 SDValue False = N->getOperand(3);
957 SDValue CC = N->getOperand(4);
959 if (VT != MVT::f32 ||
960 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
964 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
978 llvm_unreachable("Operation should already be optimised!");
985 unsigned Opc = (LHS == True) ? AMDGPUISD::FMIN : AMDGPUISD::FMAX;
986 return DAG.getNode(Opc, DL, VT, LHS, RHS);
994 unsigned Opc = (LHS == True) ? AMDGPUISD::FMAX : AMDGPUISD::FMIN;
995 return DAG.getNode(Opc, DL, VT, LHS, RHS);
997 case ISD::SETCC_INVALID:
998 llvm_unreachable("Invalid setcc condcode!");
1003 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue &Op,
1004 SelectionDAG &DAG) const {
1005 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
1006 EVT MemEltVT = Load->getMemoryVT().getVectorElementType();
1007 EVT EltVT = Op.getValueType().getVectorElementType();
1008 EVT PtrVT = Load->getBasePtr().getValueType();
1009 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1010 SmallVector<SDValue, 8> Loads;
1013 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1014 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1015 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8), PtrVT));
1016 Loads.push_back(DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1017 Load->getChain(), Ptr,
1018 MachinePointerInfo(Load->getMemOperand()->getValue()),
1019 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1020 Load->getAlignment()));
1022 return DAG.getNode(ISD::BUILD_VECTOR, SL, Op.getValueType(), Loads);
1025 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1026 SelectionDAG &DAG) const {
1027 StoreSDNode *Store = cast<StoreSDNode>(Op);
1028 EVT MemVT = Store->getMemoryVT();
1029 unsigned MemBits = MemVT.getSizeInBits();
1031 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1032 // truncating store into an i32 store.
1033 // XXX: We could also handle optimize other vector bitwidths.
1034 if (!MemVT.isVector() || MemBits > 32) {
1039 SDValue Value = Store->getValue();
1040 EVT VT = Value.getValueType();
1041 EVT ElemVT = VT.getVectorElementType();
1042 SDValue Ptr = Store->getBasePtr();
1043 EVT MemEltVT = MemVT.getVectorElementType();
1044 unsigned MemEltBits = MemEltVT.getSizeInBits();
1045 unsigned MemNumElements = MemVT.getVectorNumElements();
1046 unsigned PackedSize = MemVT.getStoreSizeInBits();
1047 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
1049 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1051 SDValue PackedValue;
1052 for (unsigned i = 0; i < MemNumElements; ++i) {
1053 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1054 DAG.getConstant(i, MVT::i32));
1055 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1056 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1058 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
1059 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1064 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1068 if (PackedSize < 32) {
1069 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1070 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1071 Store->getMemOperand()->getPointerInfo(),
1073 Store->isNonTemporal(), Store->isVolatile(),
1074 Store->getAlignment());
1077 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1078 Store->getMemOperand()->getPointerInfo(),
1079 Store->isVolatile(), Store->isNonTemporal(),
1080 Store->getAlignment());
1083 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1084 SelectionDAG &DAG) const {
1085 StoreSDNode *Store = cast<StoreSDNode>(Op);
1086 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1087 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1088 EVT PtrVT = Store->getBasePtr().getValueType();
1089 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1092 SmallVector<SDValue, 8> Chains;
1094 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1095 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1096 Store->getValue(), DAG.getConstant(i, MVT::i32));
1097 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT,
1098 Store->getBasePtr(),
1099 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8),
1101 Chains.push_back(DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1102 MachinePointerInfo(Store->getMemOperand()->getValue()),
1103 MemEltVT, Store->isVolatile(), Store->isNonTemporal(),
1104 Store->getAlignment()));
1106 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1109 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1111 LoadSDNode *Load = cast<LoadSDNode>(Op);
1112 ISD::LoadExtType ExtType = Load->getExtensionType();
1113 EVT VT = Op.getValueType();
1114 EVT MemVT = Load->getMemoryVT();
1116 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
1117 // We can do the extload to 32-bits, and then need to separately extend to
1120 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
1124 Load->getMemOperand());
1125 return DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32);
1128 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1129 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1130 // FIXME: Copied from PPC
1131 // First, load into 32 bits, then truncate to 1 bit.
1133 SDValue Chain = Load->getChain();
1134 SDValue BasePtr = Load->getBasePtr();
1135 MachineMemOperand *MMO = Load->getMemOperand();
1137 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1138 BasePtr, MVT::i8, MMO);
1139 return DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD);
1142 // Lower loads constant address space global variable loads
1143 if (Load->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
1144 isa<GlobalVariable>(
1145 GetUnderlyingObject(Load->getMemOperand()->getValue()))) {
1147 SDValue Ptr = DAG.getZExtOrTrunc(Load->getBasePtr(), DL,
1148 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
1149 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1150 DAG.getConstant(2, MVT::i32));
1151 return DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1152 Load->getChain(), Ptr,
1153 DAG.getTargetConstant(0, MVT::i32), Op.getOperand(2));
1156 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1157 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1161 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1162 DAG.getConstant(2, MVT::i32));
1163 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1164 Load->getChain(), Ptr,
1165 DAG.getTargetConstant(0, MVT::i32),
1167 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1169 DAG.getConstant(0x3, MVT::i32));
1170 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1171 DAG.getConstant(3, MVT::i32));
1173 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1175 EVT MemEltVT = MemVT.getScalarType();
1176 if (ExtType == ISD::SEXTLOAD) {
1177 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1178 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode);
1181 return DAG.getZeroExtendInReg(Ret, DL, MemEltVT);
1184 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1186 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1187 if (Result.getNode()) {
1191 StoreSDNode *Store = cast<StoreSDNode>(Op);
1192 SDValue Chain = Store->getChain();
1193 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1194 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1195 Store->getValue().getValueType().isVector()) {
1196 return SplitVectorStore(Op, DAG);
1199 EVT MemVT = Store->getMemoryVT();
1200 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1201 MemVT.bitsLT(MVT::i32)) {
1203 if (Store->getMemoryVT() == MVT::i8) {
1205 } else if (Store->getMemoryVT() == MVT::i16) {
1208 SDValue BasePtr = Store->getBasePtr();
1209 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1210 DAG.getConstant(2, MVT::i32));
1211 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1212 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1214 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1215 DAG.getConstant(0x3, MVT::i32));
1217 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1218 DAG.getConstant(3, MVT::i32));
1220 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1223 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1225 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1226 MaskedValue, ShiftAmt);
1228 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1230 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1231 DAG.getConstant(0xffffffff, MVT::i32));
1232 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1234 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1235 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1236 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1241 SDValue AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const {
1243 EVT OVT = Op.getValueType();
1244 SDValue LHS = Op.getOperand(0);
1245 SDValue RHS = Op.getOperand(1);
1248 if (!OVT.isVector()) {
1251 } else if (OVT.getVectorNumElements() == 2) {
1254 } else if (OVT.getVectorNumElements() == 4) {
1258 unsigned bitsize = OVT.getScalarType().getSizeInBits();
1259 // char|short jq = ia ^ ib;
1260 SDValue jq = DAG.getNode(ISD::XOR, DL, OVT, LHS, RHS);
1262 // jq = jq >> (bitsize - 2)
1263 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));
1266 jq = DAG.getNode(ISD::OR, DL, OVT, jq, DAG.getConstant(1, OVT));
1269 jq = DAG.getSExtOrTrunc(jq, DL, INTTY);
1271 // int ia = (int)LHS;
1272 SDValue ia = DAG.getSExtOrTrunc(LHS, DL, INTTY);
1274 // int ib, (int)RHS;
1275 SDValue ib = DAG.getSExtOrTrunc(RHS, DL, INTTY);
1277 // float fa = (float)ia;
1278 SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia);
1280 // float fb = (float)ib;
1281 SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib);
1283 // float fq = native_divide(fa, fb);
1284 SDValue fq = DAG.getNode(ISD::FMUL, DL, FLTTY,
1285 fa, DAG.getNode(AMDGPUISD::RCP, DL, FLTTY, fb));
1288 fq = DAG.getNode(ISD::FTRUNC, DL, FLTTY, fq);
1290 // float fqneg = -fq;
1291 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FLTTY, fq);
1293 // float fr = mad(fqneg, fb, fa);
1294 SDValue fr = DAG.getNode(ISD::FADD, DL, FLTTY,
1295 DAG.getNode(ISD::MUL, DL, FLTTY, fqneg, fb), fa);
1297 // int iq = (int)fq;
1298 SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq);
1301 fr = DAG.getNode(ISD::FABS, DL, FLTTY, fr);
1304 fb = DAG.getNode(ISD::FABS, DL, FLTTY, fb);
1306 // int cv = fr >= fb;
1308 if (INTTY == MVT::i32) {
1309 cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);
1311 cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);
1313 // jq = (cv ? jq : 0);
1314 jq = DAG.getNode(ISD::SELECT, DL, OVT, cv, jq,
1315 DAG.getConstant(0, OVT));
1317 iq = DAG.getSExtOrTrunc(iq, DL, OVT);
1318 iq = DAG.getNode(ISD::ADD, DL, OVT, iq, jq);
1322 SDValue AMDGPUTargetLowering::LowerSDIV32(SDValue Op, SelectionDAG &DAG) const {
1324 EVT OVT = Op.getValueType();
1325 SDValue LHS = Op.getOperand(0);
1326 SDValue RHS = Op.getOperand(1);
1327 // The LowerSDIV32 function generates equivalent to the following IL.
1337 // ixor r10, r10, r11
1339 // ixor DST, r0, r10
1348 SDValue r10 = DAG.getSelectCC(DL,
1349 r0, DAG.getConstant(0, OVT),
1350 DAG.getConstant(-1, OVT),
1351 DAG.getConstant(0, OVT),
1355 SDValue r11 = DAG.getSelectCC(DL,
1356 r1, DAG.getConstant(0, OVT),
1357 DAG.getConstant(-1, OVT),
1358 DAG.getConstant(0, OVT),
1362 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1365 r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);
1368 r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1371 r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
1374 r0 = DAG.getNode(ISD::UDIV, DL, OVT, r0, r1);
1376 // ixor r10, r10, r11
1377 r10 = DAG.getNode(ISD::XOR, DL, OVT, r10, r11);
1380 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1382 // ixor DST, r0, r10
1383 SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1387 SDValue AMDGPUTargetLowering::LowerSDIV64(SDValue Op, SelectionDAG &DAG) const {
1388 return SDValue(Op.getNode(), 0);
1391 SDValue AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
1392 EVT OVT = Op.getValueType().getScalarType();
1394 if (OVT == MVT::i64)
1395 return LowerSDIV64(Op, DAG);
1397 if (OVT.getScalarType() == MVT::i32)
1398 return LowerSDIV32(Op, DAG);
1400 if (OVT == MVT::i16 || OVT == MVT::i8) {
1401 // FIXME: We should be checking for the masked bits. This isn't reached
1402 // because i8 and i16 are not legal types.
1403 return LowerSDIV24(Op, DAG);
1406 return SDValue(Op.getNode(), 0);
1409 SDValue AMDGPUTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const {
1411 EVT OVT = Op.getValueType();
1412 SDValue LHS = Op.getOperand(0);
1413 SDValue RHS = Op.getOperand(1);
1414 // The LowerSREM32 function generates equivalent to the following IL.
1424 // umul r20, r20, r1
1427 // ixor DST, r0, r10
1436 SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT);
1439 SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT);
1442 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1445 r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);
1448 r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1451 r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
1454 SDValue r20 = DAG.getNode(ISD::UREM, DL, OVT, r0, r1);
1456 // umul r20, r20, r1
1457 r20 = DAG.getNode(AMDGPUISD::UMUL, DL, OVT, r20, r1);
1460 r0 = DAG.getNode(ISD::SUB, DL, OVT, r0, r20);
1463 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1465 // ixor DST, r0, r10
1466 SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1470 SDValue AMDGPUTargetLowering::LowerSREM64(SDValue Op, SelectionDAG &DAG) const {
1471 return SDValue(Op.getNode(), 0);
1474 SDValue AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const {
1475 EVT OVT = Op.getValueType();
1477 if (OVT.getScalarType() == MVT::i64)
1478 return LowerSREM64(Op, DAG);
1480 if (OVT.getScalarType() == MVT::i32)
1481 return LowerSREM32(Op, DAG);
1483 return SDValue(Op.getNode(), 0);
1486 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1487 SelectionDAG &DAG) const {
1489 EVT VT = Op.getValueType();
1491 SDValue Num = Op.getOperand(0);
1492 SDValue Den = Op.getOperand(1);
1494 // RCP = URECIP(Den) = 2^32 / Den + e
1495 // e is rounding error.
1496 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1498 // RCP_LO = umulo(RCP, Den) */
1499 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
1501 // RCP_HI = mulhu (RCP, Den) */
1502 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1504 // NEG_RCP_LO = -RCP_LO
1505 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1508 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1509 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1512 // Calculate the rounding error from the URECIP instruction
1513 // E = mulhu(ABS_RCP_LO, RCP)
1514 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1516 // RCP_A_E = RCP + E
1517 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1519 // RCP_S_E = RCP - E
1520 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1522 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1523 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1526 // Quotient = mulhu(Tmp0, Num)
1527 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1529 // Num_S_Remainder = Quotient * Den
1530 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
1532 // Remainder = Num - Num_S_Remainder
1533 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1535 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1536 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1537 DAG.getConstant(-1, VT),
1538 DAG.getConstant(0, VT),
1540 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1541 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1543 DAG.getConstant(-1, VT),
1544 DAG.getConstant(0, VT),
1546 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1547 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1550 // Calculate Division result:
1552 // Quotient_A_One = Quotient + 1
1553 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1554 DAG.getConstant(1, VT));
1556 // Quotient_S_One = Quotient - 1
1557 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1558 DAG.getConstant(1, VT));
1560 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1561 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1562 Quotient, Quotient_A_One, ISD::SETEQ);
1564 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1565 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1566 Quotient_S_One, Div, ISD::SETEQ);
1568 // Calculate Rem result:
1570 // Remainder_S_Den = Remainder - Den
1571 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1573 // Remainder_A_Den = Remainder + Den
1574 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1576 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1577 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1578 Remainder, Remainder_S_Den, ISD::SETEQ);
1580 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1581 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1582 Remainder_A_Den, Rem, ISD::SETEQ);
1587 return DAG.getMergeValues(Ops, DL);
1590 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1591 SelectionDAG &DAG) const {
1593 EVT VT = Op.getValueType();
1595 SDValue Zero = DAG.getConstant(0, VT);
1596 SDValue NegOne = DAG.getConstant(-1, VT);
1598 SDValue LHS = Op.getOperand(0);
1599 SDValue RHS = Op.getOperand(1);
1601 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1602 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1603 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1604 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1606 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1607 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1609 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1610 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1612 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1613 SDValue Rem = Div.getValue(1);
1615 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1616 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1618 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1619 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1625 return DAG.getMergeValues(Res, DL);
1628 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1630 SDValue Src = Op.getOperand(0);
1632 // result = trunc(src)
1633 // if (src > 0.0 && src != result)
1636 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1638 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1639 const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
1641 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1643 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1644 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1645 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1647 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1648 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1651 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1653 SDValue Src = Op.getOperand(0);
1655 assert(Op.getValueType() == MVT::f64);
1657 const SDValue Zero = DAG.getConstant(0, MVT::i32);
1658 const SDValue One = DAG.getConstant(1, MVT::i32);
1660 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1662 // Extract the upper half, since this is where we will find the sign and
1664 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1666 const unsigned FractBits = 52;
1667 const unsigned ExpBits = 11;
1669 // Extract the exponent.
1670 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_I32, SL, MVT::i32,
1672 DAG.getConstant(FractBits - 32, MVT::i32),
1673 DAG.getConstant(ExpBits, MVT::i32));
1674 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1675 DAG.getConstant(1023, MVT::i32));
1677 // Extract the sign bit.
1678 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32);
1679 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1681 // Extend back to to 64-bits.
1682 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1684 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1686 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1687 const SDValue FractMask
1688 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64);
1690 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1691 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1692 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1694 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
1696 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, MVT::i32);
1698 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1699 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1701 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1702 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1704 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1707 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1709 SDValue Src = Op.getOperand(0);
1711 assert(Op.getValueType() == MVT::f64);
1713 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
1714 SDValue C1 = DAG.getConstantFP(C1Val, MVT::f64);
1715 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
1717 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
1718 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
1720 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
1722 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
1723 SDValue C2 = DAG.getConstantFP(C2Val, MVT::f64);
1725 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1726 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
1728 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
1731 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
1732 // FNEARBYINT and FRINT are the same, except in their handling of FP
1733 // exceptions. Those aren't really meaningful for us, and OpenCL only has
1734 // rint, so just treat them as equivalent.
1735 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
1738 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
1740 SDValue Src = Op.getOperand(0);
1742 // result = trunc(src);
1743 // if (src < 0.0 && src != result)
1746 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1748 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1749 const SDValue NegOne = DAG.getConstantFP(-1.0, MVT::f64);
1751 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1753 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
1754 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1755 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1757 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
1758 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1761 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
1762 SelectionDAG &DAG) const {
1763 SDValue S0 = Op.getOperand(0);
1765 if (Op.getValueType() != MVT::f32 || S0.getValueType() != MVT::i64)
1768 // f32 uint_to_fp i64
1769 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1770 DAG.getConstant(0, MVT::i32));
1771 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
1772 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1773 DAG.getConstant(1, MVT::i32));
1774 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
1775 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
1776 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
1777 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
1780 SDValue AMDGPUTargetLowering::ExpandSIGN_EXTEND_INREG(SDValue Op,
1782 SelectionDAG &DAG) const {
1783 MVT VT = Op.getSimpleValueType();
1785 SDValue Shift = DAG.getConstant(BitsDiff, VT);
1786 // Shift left by 'Shift' bits.
1787 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Op.getOperand(0), Shift);
1788 // Signed shift Right by 'Shift' bits.
1789 return DAG.getNode(ISD::SRA, DL, VT, Shl, Shift);
1792 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
1793 SelectionDAG &DAG) const {
1794 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1795 MVT VT = Op.getSimpleValueType();
1796 MVT ScalarVT = VT.getScalarType();
1801 SDValue Src = Op.getOperand(0);
1804 // TODO: Don't scalarize on Evergreen?
1805 unsigned NElts = VT.getVectorNumElements();
1806 SmallVector<SDValue, 8> Args;
1807 DAG.ExtractVectorElements(Src, Args, 0, NElts);
1809 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
1810 for (unsigned I = 0; I < NElts; ++I)
1811 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
1813 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
1816 //===----------------------------------------------------------------------===//
1817 // Custom DAG optimizations
1818 //===----------------------------------------------------------------------===//
1820 static bool isU24(SDValue Op, SelectionDAG &DAG) {
1821 APInt KnownZero, KnownOne;
1822 EVT VT = Op.getValueType();
1823 DAG.computeKnownBits(Op, KnownZero, KnownOne);
1825 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
1828 static bool isI24(SDValue Op, SelectionDAG &DAG) {
1829 EVT VT = Op.getValueType();
1831 // In order for this to be a signed 24-bit value, bit 23, must
1833 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
1834 // as unsigned 24-bit values.
1835 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
1838 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
1840 SelectionDAG &DAG = DCI.DAG;
1841 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1842 EVT VT = Op.getValueType();
1844 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
1845 APInt KnownZero, KnownOne;
1846 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
1847 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
1848 DCI.CommitTargetLoweringOpt(TLO);
1851 template <typename IntTy>
1852 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
1853 uint32_t Offset, uint32_t Width) {
1854 if (Width + Offset < 32) {
1855 IntTy Result = (Src0 << (32 - Offset - Width)) >> (32 - Width);
1856 return DAG.getConstant(Result, MVT::i32);
1859 return DAG.getConstant(Src0 >> Offset, MVT::i32);
1862 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
1863 DAGCombinerInfo &DCI) const {
1864 EVT VT = N->getValueType(0);
1866 if (VT.isVector() || VT.getSizeInBits() > 32)
1869 SelectionDAG &DAG = DCI.DAG;
1872 SDValue N0 = N->getOperand(0);
1873 SDValue N1 = N->getOperand(1);
1876 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
1877 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
1878 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
1879 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
1880 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
1881 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
1882 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
1883 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
1888 // We need to use sext even for MUL_U24, because MUL_U24 is used
1889 // for signed multiply of 8 and 16-bit types.
1890 return DAG.getSExtOrTrunc(Mul, DL, VT);
1893 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
1894 DAGCombinerInfo &DCI) const {
1895 SelectionDAG &DAG = DCI.DAG;
1898 switch(N->getOpcode()) {
1901 return performMulCombine(N, DCI);
1902 case AMDGPUISD::MUL_I24:
1903 case AMDGPUISD::MUL_U24: {
1904 SDValue N0 = N->getOperand(0);
1905 SDValue N1 = N->getOperand(1);
1906 simplifyI24(N0, DCI);
1907 simplifyI24(N1, DCI);
1910 case ISD::SELECT_CC: {
1911 return CombineMinMax(N, DAG);
1913 case AMDGPUISD::BFE_I32:
1914 case AMDGPUISD::BFE_U32: {
1915 assert(!N->getValueType(0).isVector() &&
1916 "Vector handling of BFE not implemented");
1917 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
1921 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
1923 return DAG.getConstant(0, MVT::i32);
1925 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
1929 SDValue BitsFrom = N->getOperand(0);
1930 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
1932 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
1934 if (OffsetVal == 0) {
1935 // This is already sign / zero extended, so try to fold away extra BFEs.
1936 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
1938 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
1939 if (OpSignBits >= SignBits)
1942 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
1944 // This is a sign_extend_inreg. Replace it to take advantage of existing
1945 // DAG Combines. If not eliminated, we will match back to BFE during
1948 // TODO: The sext_inreg of extended types ends, although we can could
1949 // handle them in a single BFE.
1950 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
1951 DAG.getValueType(SmallVT));
1954 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
1957 if (ConstantSDNode *Val = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
1959 return constantFoldBFE<int32_t>(DAG,
1960 Val->getSExtValue(),
1965 return constantFoldBFE<uint32_t>(DAG,
1966 Val->getZExtValue(),
1971 APInt Demanded = APInt::getBitsSet(32,
1973 OffsetVal + WidthVal);
1975 if ((OffsetVal + WidthVal) >= 32) {
1976 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
1977 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
1978 BitsFrom, ShiftVal);
1981 APInt KnownZero, KnownOne;
1982 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1983 !DCI.isBeforeLegalizeOps());
1984 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1985 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
1986 TLI.SimplifyDemandedBits(BitsFrom, Demanded, KnownZero, KnownOne, TLO)) {
1987 DCI.CommitTargetLoweringOpt(TLO);
1996 //===----------------------------------------------------------------------===//
1998 //===----------------------------------------------------------------------===//
2000 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2003 const SmallVectorImpl<ISD::InputArg> &Ins,
2004 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2006 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2007 if (Ins[i].ArgVT == Ins[i].VT) {
2008 OrigIns.push_back(Ins[i]);
2013 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2014 // Vector has been split into scalars.
2015 VT = Ins[i].ArgVT.getVectorElementType();
2016 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2017 Ins[i].ArgVT.getVectorElementType() !=
2018 Ins[i].VT.getVectorElementType()) {
2019 // Vector elements have been promoted
2022 // Vector has been spilt into smaller vectors.
2026 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2027 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2028 OrigIns.push_back(Arg);
2032 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2033 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2034 return CFP->isExactlyValue(1.0);
2036 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2037 return C->isAllOnesValue();
2042 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2043 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2044 return CFP->getValueAPF().isZero();
2046 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2047 return C->isNullValue();
2052 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2053 const TargetRegisterClass *RC,
2054 unsigned Reg, EVT VT) const {
2055 MachineFunction &MF = DAG.getMachineFunction();
2056 MachineRegisterInfo &MRI = MF.getRegInfo();
2057 unsigned VirtualRegister;
2058 if (!MRI.isLiveIn(Reg)) {
2059 VirtualRegister = MRI.createVirtualRegister(RC);
2060 MRI.addLiveIn(Reg, VirtualRegister);
2062 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2064 return DAG.getRegister(VirtualRegister, VT);
2067 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2069 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2071 default: return nullptr;
2073 NODE_NAME_CASE(CALL);
2074 NODE_NAME_CASE(UMUL);
2075 NODE_NAME_CASE(RET_FLAG);
2076 NODE_NAME_CASE(BRANCH_COND);
2079 NODE_NAME_CASE(DWORDADDR)
2080 NODE_NAME_CASE(FRACT)
2081 NODE_NAME_CASE(CLAMP)
2082 NODE_NAME_CASE(FMAX)
2083 NODE_NAME_CASE(SMAX)
2084 NODE_NAME_CASE(UMAX)
2085 NODE_NAME_CASE(FMIN)
2086 NODE_NAME_CASE(SMIN)
2087 NODE_NAME_CASE(UMIN)
2088 NODE_NAME_CASE(URECIP)
2089 NODE_NAME_CASE(DIV_SCALE)
2090 NODE_NAME_CASE(DIV_FMAS)
2091 NODE_NAME_CASE(DIV_FIXUP)
2092 NODE_NAME_CASE(TRIG_PREOP)
2095 NODE_NAME_CASE(RSQ_LEGACY)
2096 NODE_NAME_CASE(RSQ_CLAMPED)
2097 NODE_NAME_CASE(DOT4)
2098 NODE_NAME_CASE(BFE_U32)
2099 NODE_NAME_CASE(BFE_I32)
2102 NODE_NAME_CASE(BREV)
2103 NODE_NAME_CASE(MUL_U24)
2104 NODE_NAME_CASE(MUL_I24)
2105 NODE_NAME_CASE(MAD_U24)
2106 NODE_NAME_CASE(MAD_I24)
2107 NODE_NAME_CASE(EXPORT)
2108 NODE_NAME_CASE(CONST_ADDRESS)
2109 NODE_NAME_CASE(REGISTER_LOAD)
2110 NODE_NAME_CASE(REGISTER_STORE)
2111 NODE_NAME_CASE(LOAD_CONSTANT)
2112 NODE_NAME_CASE(LOAD_INPUT)
2113 NODE_NAME_CASE(SAMPLE)
2114 NODE_NAME_CASE(SAMPLEB)
2115 NODE_NAME_CASE(SAMPLED)
2116 NODE_NAME_CASE(SAMPLEL)
2117 NODE_NAME_CASE(CVT_F32_UBYTE0)
2118 NODE_NAME_CASE(CVT_F32_UBYTE1)
2119 NODE_NAME_CASE(CVT_F32_UBYTE2)
2120 NODE_NAME_CASE(CVT_F32_UBYTE3)
2121 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2122 NODE_NAME_CASE(STORE_MSKOR)
2123 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2127 static void computeKnownBitsForMinMax(const SDValue Op0,
2131 const SelectionDAG &DAG,
2133 APInt Op0Zero, Op0One;
2134 APInt Op1Zero, Op1One;
2135 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2136 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2138 KnownZero = Op0Zero & Op1Zero;
2139 KnownOne = Op0One & Op1One;
2142 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2146 const SelectionDAG &DAG,
2147 unsigned Depth) const {
2149 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2153 unsigned Opc = Op.getOpcode();
2158 case ISD::INTRINSIC_WO_CHAIN: {
2159 // FIXME: The intrinsic should just use the node.
2160 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2161 case AMDGPUIntrinsic::AMDGPU_imax:
2162 case AMDGPUIntrinsic::AMDGPU_umax:
2163 case AMDGPUIntrinsic::AMDGPU_imin:
2164 case AMDGPUIntrinsic::AMDGPU_umin:
2165 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2166 KnownZero, KnownOne, DAG, Depth);
2174 case AMDGPUISD::SMAX:
2175 case AMDGPUISD::UMAX:
2176 case AMDGPUISD::SMIN:
2177 case AMDGPUISD::UMIN:
2178 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
2179 KnownZero, KnownOne, DAG, Depth);
2182 case AMDGPUISD::BFE_I32:
2183 case AMDGPUISD::BFE_U32: {
2184 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2188 unsigned BitWidth = 32;
2189 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2191 KnownZero = APInt::getAllOnesValue(BitWidth);
2192 KnownOne = APInt::getNullValue(BitWidth);
2196 // FIXME: This could do a lot more. If offset is 0, should be the same as
2197 // sign_extend_inreg implementation, but that involves duplicating it.
2198 if (Opc == AMDGPUISD::BFE_I32)
2199 KnownOne = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2201 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2208 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2210 const SelectionDAG &DAG,
2211 unsigned Depth) const {
2212 switch (Op.getOpcode()) {
2213 case AMDGPUISD::BFE_I32: {
2214 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2218 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2219 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2220 if (!Offset || !Offset->isNullValue())
2223 // TODO: Could probably figure something out with non-0 offsets.
2224 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2225 return std::max(SignBits, Op0SignBits);
2228 case AMDGPUISD::BFE_U32: {
2229 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2230 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;