1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPURegisterInfo.h"
20 #include "AMDGPUSubtarget.h"
21 #include "AMDILIntrinsicInfo.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/DataLayout.h"
33 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
34 CCValAssign::LocInfo LocInfo,
35 ISD::ArgFlagsTy ArgFlags, CCState &State) {
36 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
37 ArgFlags.getOrigAlign());
38 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
43 #include "AMDGPUGenCallingConv.inc"
45 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
46 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
48 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
50 // Initialize target lowering borrowed from AMDIL
53 // We need to custom lower some of the intrinsics
54 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
56 // Library functions. These default to Expand, but we have instructions
58 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
59 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
60 setOperationAction(ISD::FPOW, MVT::f32, Legal);
61 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
62 setOperationAction(ISD::FABS, MVT::f32, Legal);
63 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
64 setOperationAction(ISD::FRINT, MVT::f32, Legal);
65 setOperationAction(ISD::FROUND, MVT::f32, Legal);
66 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
68 // The hardware supports ROTR, but not ROTL
69 setOperationAction(ISD::ROTL, MVT::i32, Expand);
71 // Lower floating point store/load to integer store/load to reduce the number
72 // of patterns in tablegen.
73 setOperationAction(ISD::STORE, MVT::f32, Promote);
74 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
76 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
77 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
79 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
80 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
82 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
83 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
85 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
86 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
88 setOperationAction(ISD::STORE, MVT::f64, Promote);
89 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
91 // Custom lowering of vector stores is required for local address space
93 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
94 // XXX: Native v2i32 local address space stores are possible, but not
95 // currently implemented.
96 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
98 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
99 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
100 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
102 // XXX: This can be change to Custom, once ExpandVectorStores can
103 // handle 64-bit stores.
104 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
106 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
107 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
108 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
111 setOperationAction(ISD::LOAD, MVT::f32, Promote);
112 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
114 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
115 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
117 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
118 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
120 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
121 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
123 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
124 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
126 setOperationAction(ISD::LOAD, MVT::f64, Promote);
127 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
129 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
130 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
131 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
132 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
133 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
134 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
135 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
136 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
137 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
138 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
140 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
141 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
142 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
143 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
144 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
145 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
146 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
147 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
148 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
149 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
150 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
151 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
153 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
155 setOperationAction(ISD::FNEG, MVT::v2f32, Expand);
156 setOperationAction(ISD::FNEG, MVT::v4f32, Expand);
158 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
160 setOperationAction(ISD::MUL, MVT::i64, Expand);
162 setOperationAction(ISD::UDIV, MVT::i32, Expand);
163 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
164 setOperationAction(ISD::UREM, MVT::i32, Expand);
165 setOperationAction(ISD::VSELECT, MVT::v2f32, Expand);
166 setOperationAction(ISD::VSELECT, MVT::v4f32, Expand);
168 static const MVT::SimpleValueType IntTypes[] = {
169 MVT::v2i32, MVT::v4i32
171 const size_t NumIntTypes = array_lengthof(IntTypes);
173 for (unsigned int x = 0; x < NumIntTypes; ++x) {
174 MVT::SimpleValueType VT = IntTypes[x];
175 //Expand the following operations for the current type by default
176 setOperationAction(ISD::ADD, VT, Expand);
177 setOperationAction(ISD::AND, VT, Expand);
178 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
179 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
180 setOperationAction(ISD::MUL, VT, Expand);
181 setOperationAction(ISD::OR, VT, Expand);
182 setOperationAction(ISD::SHL, VT, Expand);
183 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
184 setOperationAction(ISD::SRL, VT, Expand);
185 setOperationAction(ISD::SRA, VT, Expand);
186 setOperationAction(ISD::SUB, VT, Expand);
187 setOperationAction(ISD::UDIV, VT, Expand);
188 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
189 setOperationAction(ISD::UREM, VT, Expand);
190 setOperationAction(ISD::SELECT, VT, Expand);
191 setOperationAction(ISD::VSELECT, VT, Expand);
192 setOperationAction(ISD::XOR, VT, Expand);
195 static const MVT::SimpleValueType FloatTypes[] = {
196 MVT::v2f32, MVT::v4f32
198 const size_t NumFloatTypes = array_lengthof(FloatTypes);
200 for (unsigned int x = 0; x < NumFloatTypes; ++x) {
201 MVT::SimpleValueType VT = FloatTypes[x];
202 setOperationAction(ISD::FABS, VT, Expand);
203 setOperationAction(ISD::FADD, VT, Expand);
204 setOperationAction(ISD::FDIV, VT, Expand);
205 setOperationAction(ISD::FPOW, VT, Expand);
206 setOperationAction(ISD::FFLOOR, VT, Expand);
207 setOperationAction(ISD::FTRUNC, VT, Expand);
208 setOperationAction(ISD::FMUL, VT, Expand);
209 setOperationAction(ISD::FRINT, VT, Expand);
210 setOperationAction(ISD::FSQRT, VT, Expand);
211 setOperationAction(ISD::FSUB, VT, Expand);
212 setOperationAction(ISD::SELECT, VT, Expand);
215 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom);
216 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
217 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
219 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Custom);
220 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
221 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
223 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Custom);
224 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
225 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
227 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Custom);
229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
232 //===----------------------------------------------------------------------===//
233 // Target Information
234 //===----------------------------------------------------------------------===//
236 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
240 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
242 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
245 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
246 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
248 return ((LScalarSize <= CastScalarSize) ||
249 (CastScalarSize >= 32) ||
253 //===---------------------------------------------------------------------===//
255 //===---------------------------------------------------------------------===//
257 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
258 assert(VT.isFloatingPoint());
259 return VT == MVT::f32;
262 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
263 assert(VT.isFloatingPoint());
264 return VT == MVT::f32;
267 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
268 // Truncate is just accessing a subregister.
269 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
272 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
273 // Truncate is just accessing a subregister.
274 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
275 (Dest->getPrimitiveSizeInBits() % 32 == 0);
278 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
279 const DataLayout *DL = getDataLayout();
280 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
281 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
283 return SrcSize == 32 && DestSize == 64;
286 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
287 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
288 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
289 // this will enable reducing 64-bit operations the 32-bit, which is always
291 return Src == MVT::i32 && Dest == MVT::i64;
294 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
295 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
296 // limited number of native 64-bit operations. Shrinking an operation to fit
297 // in a single 32-bit register should always be helpful. As currently used,
298 // this is much less general than the name suggests, and is only used in
299 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
300 // not profitable, and may actually be harmful.
301 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
304 //===---------------------------------------------------------------------===//
305 // TargetLowering Callbacks
306 //===---------------------------------------------------------------------===//
308 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
309 const SmallVectorImpl<ISD::InputArg> &Ins) const {
311 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
314 SDValue AMDGPUTargetLowering::LowerReturn(
316 CallingConv::ID CallConv,
318 const SmallVectorImpl<ISD::OutputArg> &Outs,
319 const SmallVectorImpl<SDValue> &OutVals,
320 SDLoc DL, SelectionDAG &DAG) const {
321 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
324 //===---------------------------------------------------------------------===//
325 // Target specific lowering
326 //===---------------------------------------------------------------------===//
328 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
330 switch (Op.getOpcode()) {
332 Op.getNode()->dump();
333 llvm_unreachable("Custom lowering code for this"
334 "instruction is not implemented yet!");
336 // AMDIL DAG lowering
337 case ISD::SDIV: return LowerSDIV(Op, DAG);
338 case ISD::SREM: return LowerSREM(Op, DAG);
339 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
340 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
341 // AMDGPU DAG lowering
342 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
343 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
344 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
345 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
346 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
347 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
352 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
353 SmallVectorImpl<SDValue> &Results,
354 SelectionDAG &DAG) const {
355 switch (N->getOpcode()) {
356 case ISD::SIGN_EXTEND_INREG:
357 // Different parts of legalization seem to interpret which type of
358 // sign_extend_inreg is the one to check for custom lowering. The extended
359 // from type is what really matters, but some places check for custom
360 // lowering of the result type. This results in trying to use
361 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
362 // nothing here and let the illegal result integer be handled normally.
370 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
371 const GlobalValue *GV,
372 const SDValue &InitPtr,
374 SelectionDAG &DAG) const {
375 const DataLayout *TD = getTargetMachine().getDataLayout();
377 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
378 EVT VT = EVT::getEVT(CI->getType());
379 PointerType *PtrTy = PointerType::get(CI->getType(), 0);
380 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
381 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
382 TD->getPrefTypeAlignment(CI->getType()));
383 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
384 EVT VT = EVT::getEVT(CFP->getType());
385 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
386 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
387 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
388 TD->getPrefTypeAlignment(CFP->getType()));
389 } else if (Init->getType()->isAggregateType()) {
390 EVT PtrVT = InitPtr.getValueType();
391 unsigned NumElements = Init->getType()->getArrayNumElements();
392 SmallVector<SDValue, 8> Chains;
393 for (unsigned i = 0; i < NumElements; ++i) {
394 SDValue Offset = DAG.getConstant(i * TD->getTypeAllocSize(
395 Init->getType()->getArrayElementType()), PtrVT);
396 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
397 Chains.push_back(LowerConstantInitializer(Init->getAggregateElement(i),
398 GV, Ptr, Chain, DAG));
400 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
401 Chains.data(), Chains.size());
404 llvm_unreachable("Unhandled constant initializer");
408 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
410 SelectionDAG &DAG) const {
412 const DataLayout *TD = getTargetMachine().getDataLayout();
413 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
414 const GlobalValue *GV = G->getGlobal();
416 switch (G->getAddressSpace()) {
417 default: llvm_unreachable("Global Address lowering not implemented for this "
419 case AMDGPUAS::LOCAL_ADDRESS: {
420 // XXX: What does the value of G->getOffset() mean?
421 assert(G->getOffset() == 0 &&
422 "Do not know what to do with an non-zero offset");
425 if (MFI->LocalMemoryObjects.count(GV) == 0) {
426 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
427 Offset = MFI->LDSSize;
428 MFI->LocalMemoryObjects[GV] = Offset;
429 // XXX: Account for alignment?
430 MFI->LDSSize += Size;
432 Offset = MFI->LocalMemoryObjects[GV];
435 return DAG.getConstant(Offset, getPointerTy(G->getAddressSpace()));
437 case AMDGPUAS::CONSTANT_ADDRESS: {
438 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
439 Type *EltType = GV->getType()->getElementType();
440 unsigned Size = TD->getTypeAllocSize(EltType);
441 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
443 const GlobalVariable *Var = dyn_cast<GlobalVariable>(GV);
444 const Constant *Init = Var->getInitializer();
445 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
446 SDValue InitPtr = DAG.getFrameIndex(FI,
447 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
448 SmallVector<SDNode*, 8> WorkList;
450 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
451 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
452 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
454 WorkList.push_back(*I);
456 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
457 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
458 E = WorkList.end(); I != E; ++I) {
459 SmallVector<SDValue, 8> Ops;
460 Ops.push_back(Chain);
461 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
462 Ops.push_back((*I)->getOperand(i));
464 DAG.UpdateNodeOperands(*I, Ops.data(), Ops.size());
466 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op),
467 getPointerTy(AMDGPUAS::CONSTANT_ADDRESS));
472 void AMDGPUTargetLowering::ExtractVectorElements(SDValue Op, SelectionDAG &DAG,
473 SmallVectorImpl<SDValue> &Args,
475 unsigned Count) const {
476 EVT VT = Op.getValueType();
477 for (unsigned i = Start, e = Start + Count; i != e; ++i) {
478 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
479 VT.getVectorElementType(),
480 Op, DAG.getConstant(i, MVT::i32)));
484 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
485 SelectionDAG &DAG) const {
486 SmallVector<SDValue, 8> Args;
487 SDValue A = Op.getOperand(0);
488 SDValue B = Op.getOperand(1);
490 ExtractVectorElements(A, DAG, Args, 0,
491 A.getValueType().getVectorNumElements());
492 ExtractVectorElements(B, DAG, Args, 0,
493 B.getValueType().getVectorNumElements());
495 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(),
496 Args.data(), Args.size());
499 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
500 SelectionDAG &DAG) const {
502 SmallVector<SDValue, 8> Args;
503 EVT VT = Op.getValueType();
504 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
505 ExtractVectorElements(Op.getOperand(0), DAG, Args, Start,
506 VT.getVectorNumElements());
508 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(),
509 Args.data(), Args.size());
512 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
513 SelectionDAG &DAG) const {
515 MachineFunction &MF = DAG.getMachineFunction();
516 const AMDGPUFrameLowering *TFL =
517 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
519 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op);
522 unsigned FrameIndex = FIN->getIndex();
523 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
524 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
528 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
529 SelectionDAG &DAG) const {
530 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
532 EVT VT = Op.getValueType();
534 switch (IntrinsicID) {
536 case AMDGPUIntrinsic::AMDIL_abs:
537 return LowerIntrinsicIABS(Op, DAG);
538 case AMDGPUIntrinsic::AMDIL_exp:
539 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
540 case AMDGPUIntrinsic::AMDGPU_lrp:
541 return LowerIntrinsicLRP(Op, DAG);
542 case AMDGPUIntrinsic::AMDIL_fraction:
543 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
544 case AMDGPUIntrinsic::AMDIL_max:
545 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
547 case AMDGPUIntrinsic::AMDGPU_imax:
548 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
550 case AMDGPUIntrinsic::AMDGPU_umax:
551 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
553 case AMDGPUIntrinsic::AMDIL_min:
554 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
556 case AMDGPUIntrinsic::AMDGPU_imin:
557 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
559 case AMDGPUIntrinsic::AMDGPU_umin:
560 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
563 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
564 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
569 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
570 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
575 case AMDGPUIntrinsic::AMDGPU_bfi:
576 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
581 case AMDGPUIntrinsic::AMDGPU_bfm:
582 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
586 case AMDGPUIntrinsic::AMDIL_round_nearest:
587 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
591 ///IABS(a) = SMAX(sub(0, a), a)
592 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
593 SelectionDAG &DAG) const {
596 EVT VT = Op.getValueType();
597 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
600 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
603 /// Linear Interpolation
604 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
605 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
606 SelectionDAG &DAG) const {
608 EVT VT = Op.getValueType();
609 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
610 DAG.getConstantFP(1.0f, MVT::f32),
612 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
614 return DAG.getNode(ISD::FADD, DL, VT,
615 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
619 /// \brief Generate Min/Max node
620 SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op,
621 SelectionDAG &DAG) const {
623 EVT VT = Op.getValueType();
625 SDValue LHS = Op.getOperand(0);
626 SDValue RHS = Op.getOperand(1);
627 SDValue True = Op.getOperand(2);
628 SDValue False = Op.getOperand(3);
629 SDValue CC = Op.getOperand(4);
631 if (VT != MVT::f32 ||
632 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
636 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
650 llvm_unreachable("Operation should already be optimised!");
658 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
660 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
669 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
671 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
673 case ISD::SETCC_INVALID:
674 llvm_unreachable("Invalid setcc condcode!");
679 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue &Op,
680 SelectionDAG &DAG) const {
681 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
682 EVT MemEltVT = Load->getMemoryVT().getVectorElementType();
683 EVT EltVT = Op.getValueType().getVectorElementType();
684 EVT PtrVT = Load->getBasePtr().getValueType();
685 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
686 SmallVector<SDValue, 8> Loads;
689 for (unsigned i = 0, e = NumElts; i != e; ++i) {
690 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
691 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8), PtrVT));
692 Loads.push_back(DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
693 Load->getChain(), Ptr,
694 MachinePointerInfo(Load->getMemOperand()->getValue()),
695 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
696 Load->getAlignment()));
698 return DAG.getNode(ISD::BUILD_VECTOR, SL, Op.getValueType(),
699 Loads.data(), Loads.size());
702 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
703 SelectionDAG &DAG) const {
704 StoreSDNode *Store = dyn_cast<StoreSDNode>(Op);
705 EVT MemVT = Store->getMemoryVT();
706 unsigned MemBits = MemVT.getSizeInBits();
708 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
709 // truncating store into an i32 store.
710 // XXX: We could also handle optimize other vector bitwidths.
711 if (!MemVT.isVector() || MemBits > 32) {
716 const SDValue &Value = Store->getValue();
717 EVT VT = Value.getValueType();
718 const SDValue &Ptr = Store->getBasePtr();
719 EVT MemEltVT = MemVT.getVectorElementType();
720 unsigned MemEltBits = MemEltVT.getSizeInBits();
721 unsigned MemNumElements = MemVT.getVectorNumElements();
722 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits());
723 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, PackedVT);
726 for (unsigned i = 0; i < MemNumElements; ++i) {
727 EVT ElemVT = VT.getVectorElementType();
728 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
729 DAG.getConstant(i, MVT::i32));
730 Elt = DAG.getZExtOrTrunc(Elt, DL, PackedVT);
731 Elt = DAG.getNode(ISD::AND, DL, PackedVT, Elt, Mask);
732 SDValue Shift = DAG.getConstant(MemEltBits * i, PackedVT);
733 Elt = DAG.getNode(ISD::SHL, DL, PackedVT, Elt, Shift);
737 PackedValue = DAG.getNode(ISD::OR, DL, PackedVT, PackedValue, Elt);
740 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
741 MachinePointerInfo(Store->getMemOperand()->getValue()),
742 Store->isVolatile(), Store->isNonTemporal(),
743 Store->getAlignment());
746 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
747 SelectionDAG &DAG) const {
748 StoreSDNode *Store = cast<StoreSDNode>(Op);
749 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
750 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
751 EVT PtrVT = Store->getBasePtr().getValueType();
752 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
755 SmallVector<SDValue, 8> Chains;
757 for (unsigned i = 0, e = NumElts; i != e; ++i) {
758 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
759 Store->getValue(), DAG.getConstant(i, MVT::i32));
760 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT,
762 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8),
764 Chains.push_back(DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
765 MachinePointerInfo(Store->getMemOperand()->getValue()),
766 MemEltVT, Store->isVolatile(), Store->isNonTemporal(),
767 Store->getAlignment()));
769 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains.data(), NumElts);
772 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
774 LoadSDNode *Load = cast<LoadSDNode>(Op);
775 ISD::LoadExtType ExtType = Load->getExtensionType();
776 EVT VT = Op.getValueType();
777 EVT MemVT = Load->getMemoryVT();
779 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
780 // We can do the extload to 32-bits, and then need to separately extend to
783 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
787 Load->getMemOperand());
788 return DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32);
791 // Lower loads constant address space global variable loads
792 if (Load->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
793 isa<GlobalVariable>(GetUnderlyingObject(Load->getPointerInfo().V))) {
795 SDValue Ptr = DAG.getZExtOrTrunc(Load->getBasePtr(), DL,
796 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
797 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
798 DAG.getConstant(2, MVT::i32));
799 return DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
800 Load->getChain(), Ptr,
801 DAG.getTargetConstant(0, MVT::i32), Op.getOperand(2));
804 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
805 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
809 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
810 DAG.getConstant(2, MVT::i32));
811 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
812 Load->getChain(), Ptr,
813 DAG.getTargetConstant(0, MVT::i32),
815 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
817 DAG.getConstant(0x3, MVT::i32));
818 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
819 DAG.getConstant(3, MVT::i32));
821 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
823 EVT MemEltVT = MemVT.getScalarType();
824 if (ExtType == ISD::SEXTLOAD) {
825 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
826 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode);
829 return DAG.getZeroExtendInReg(Ret, DL, MemEltVT);
832 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
834 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
835 if (Result.getNode()) {
839 StoreSDNode *Store = cast<StoreSDNode>(Op);
840 SDValue Chain = Store->getChain();
841 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
842 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
843 Store->getValue().getValueType().isVector()) {
844 return SplitVectorStore(Op, DAG);
847 EVT MemVT = Store->getMemoryVT();
848 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
849 MemVT.bitsLT(MVT::i32)) {
851 if (Store->getMemoryVT() == MVT::i8) {
853 } else if (Store->getMemoryVT() == MVT::i16) {
856 SDValue BasePtr = Store->getBasePtr();
857 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
858 DAG.getConstant(2, MVT::i32));
859 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
860 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
862 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
863 DAG.getConstant(0x3, MVT::i32));
865 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
866 DAG.getConstant(3, MVT::i32));
868 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
871 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
873 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
874 MaskedValue, ShiftAmt);
876 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
878 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
879 DAG.getConstant(0xffffffff, MVT::i32));
880 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
882 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
883 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
884 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
889 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
890 SelectionDAG &DAG) const {
892 EVT VT = Op.getValueType();
894 SDValue Num = Op.getOperand(0);
895 SDValue Den = Op.getOperand(1);
897 SmallVector<SDValue, 8> Results;
899 // RCP = URECIP(Den) = 2^32 / Den + e
900 // e is rounding error.
901 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
903 // RCP_LO = umulo(RCP, Den) */
904 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
906 // RCP_HI = mulhu (RCP, Den) */
907 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
909 // NEG_RCP_LO = -RCP_LO
910 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
913 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
914 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
917 // Calculate the rounding error from the URECIP instruction
918 // E = mulhu(ABS_RCP_LO, RCP)
919 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
922 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
925 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
927 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
928 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
931 // Quotient = mulhu(Tmp0, Num)
932 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
934 // Num_S_Remainder = Quotient * Den
935 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
937 // Remainder = Num - Num_S_Remainder
938 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
940 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
941 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
942 DAG.getConstant(-1, VT),
943 DAG.getConstant(0, VT),
945 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
946 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
948 DAG.getConstant(-1, VT),
949 DAG.getConstant(0, VT),
951 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
952 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
955 // Calculate Division result:
957 // Quotient_A_One = Quotient + 1
958 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
959 DAG.getConstant(1, VT));
961 // Quotient_S_One = Quotient - 1
962 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
963 DAG.getConstant(1, VT));
965 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
966 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
967 Quotient, Quotient_A_One, ISD::SETEQ);
969 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
970 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
971 Quotient_S_One, Div, ISD::SETEQ);
973 // Calculate Rem result:
975 // Remainder_S_Den = Remainder - Den
976 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
978 // Remainder_A_Den = Remainder + Den
979 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
981 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
982 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
983 Remainder, Remainder_S_Den, ISD::SETEQ);
985 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
986 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
987 Remainder_A_Den, Rem, ISD::SETEQ);
992 return DAG.getMergeValues(Ops, 2, DL);
995 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
996 SelectionDAG &DAG) const {
997 SDValue S0 = Op.getOperand(0);
999 if (Op.getValueType() != MVT::f32 || S0.getValueType() != MVT::i64)
1002 // f32 uint_to_fp i64
1003 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1004 DAG.getConstant(0, MVT::i32));
1005 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
1006 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1007 DAG.getConstant(1, MVT::i32));
1008 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
1009 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
1010 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
1011 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
1015 SDValue AMDGPUTargetLowering::ExpandSIGN_EXTEND_INREG(SDValue Op,
1017 SelectionDAG &DAG) const {
1018 MVT VT = Op.getSimpleValueType();
1020 SDValue Shift = DAG.getConstant(BitsDiff, VT);
1021 // Shift left by 'Shift' bits.
1022 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Op.getOperand(0), Shift);
1023 // Signed shift Right by 'Shift' bits.
1024 return DAG.getNode(ISD::SRA, DL, VT, Shl, Shift);
1027 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
1028 SelectionDAG &DAG) const {
1029 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1030 MVT VT = Op.getSimpleValueType();
1031 MVT ScalarVT = VT.getScalarType();
1033 unsigned SrcBits = ExtraVT.getScalarType().getSizeInBits();
1034 unsigned DestBits = ScalarVT.getSizeInBits();
1035 unsigned BitsDiff = DestBits - SrcBits;
1037 if (!Subtarget->hasBFE())
1038 return ExpandSIGN_EXTEND_INREG(Op, BitsDiff, DAG);
1040 SDValue Src = Op.getOperand(0);
1041 if (VT.isVector()) {
1043 // Need to scalarize this, and revisit each of the scalars later.
1044 // TODO: Don't scalarize on Evergreen?
1045 unsigned NElts = VT.getVectorNumElements();
1046 SmallVector<SDValue, 8> Args;
1047 ExtractVectorElements(Src, DAG, Args, 0, NElts);
1049 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
1050 for (unsigned I = 0; I < NElts; ++I)
1051 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
1053 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args.data(), Args.size());
1056 if (SrcBits == 32) {
1059 // If the source is 32-bits, this is really half of a 2-register pair, and
1060 // we need to discard the unused half of the pair.
1061 SDValue TruncSrc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Src);
1062 return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, TruncSrc);
1065 unsigned NElts = VT.isVector() ? VT.getVectorNumElements() : 1;
1067 // TODO: Match 64-bit BFE. SI has a 64-bit BFE, but it's scalar only so it
1068 // might not be worth the effort, and will need to expand to shifts when
1069 // fixing SGPR copies.
1070 if (SrcBits < 32 && DestBits <= 32) {
1072 MVT ExtVT = (NElts == 1) ? MVT::i32 : MVT::getVectorVT(MVT::i32, NElts);
1075 Src = DAG.getNode(ISD::ZERO_EXTEND, DL, ExtVT, Src);
1077 // FIXME: This should use TargetConstant, but that hits assertions for
1079 SDValue Ext = DAG.getNode(AMDGPUISD::BFE_I32, DL, ExtVT,
1080 Op.getOperand(0), // Operand
1081 DAG.getConstant(0, ExtVT), // Offset
1082 DAG.getConstant(SrcBits, ExtVT)); // Width
1084 // Truncate to the original type if necessary.
1085 if (ScalarVT == MVT::i32)
1087 return DAG.getNode(ISD::TRUNCATE, DL, VT, Ext);
1090 // For small types, extend to 32-bits first.
1093 MVT ExtVT = (NElts == 1) ? MVT::i32 : MVT::getVectorVT(MVT::i32, NElts);
1095 SDValue TruncSrc = DAG.getNode(ISD::TRUNCATE, DL, ExtVT, Src);
1096 SDValue Ext32 = DAG.getNode(AMDGPUISD::BFE_I32,
1099 TruncSrc, // Operand
1100 DAG.getConstant(0, ExtVT), // Offset
1101 DAG.getConstant(SrcBits, ExtVT)); // Width
1103 return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Ext32);
1106 // For everything else, use the standard bitshift expansion.
1107 return ExpandSIGN_EXTEND_INREG(Op, BitsDiff, DAG);
1110 //===----------------------------------------------------------------------===//
1112 //===----------------------------------------------------------------------===//
1114 void AMDGPUTargetLowering::getOriginalFunctionArgs(
1117 const SmallVectorImpl<ISD::InputArg> &Ins,
1118 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
1120 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1121 if (Ins[i].ArgVT == Ins[i].VT) {
1122 OrigIns.push_back(Ins[i]);
1127 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
1128 // Vector has been split into scalars.
1129 VT = Ins[i].ArgVT.getVectorElementType();
1130 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
1131 Ins[i].ArgVT.getVectorElementType() !=
1132 Ins[i].VT.getVectorElementType()) {
1133 // Vector elements have been promoted
1136 // Vector has been spilt into smaller vectors.
1140 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
1141 Ins[i].OrigArgIndex, Ins[i].PartOffset);
1142 OrigIns.push_back(Arg);
1146 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
1147 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
1148 return CFP->isExactlyValue(1.0);
1150 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
1151 return C->isAllOnesValue();
1156 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
1157 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
1158 return CFP->getValueAPF().isZero();
1160 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
1161 return C->isNullValue();
1166 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
1167 const TargetRegisterClass *RC,
1168 unsigned Reg, EVT VT) const {
1169 MachineFunction &MF = DAG.getMachineFunction();
1170 MachineRegisterInfo &MRI = MF.getRegInfo();
1171 unsigned VirtualRegister;
1172 if (!MRI.isLiveIn(Reg)) {
1173 VirtualRegister = MRI.createVirtualRegister(RC);
1174 MRI.addLiveIn(Reg, VirtualRegister);
1176 VirtualRegister = MRI.getLiveInVirtReg(Reg);
1178 return DAG.getRegister(VirtualRegister, VT);
1181 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
1183 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
1187 NODE_NAME_CASE(CALL);
1188 NODE_NAME_CASE(UMUL);
1189 NODE_NAME_CASE(DIV_INF);
1190 NODE_NAME_CASE(RET_FLAG);
1191 NODE_NAME_CASE(BRANCH_COND);
1194 NODE_NAME_CASE(DWORDADDR)
1195 NODE_NAME_CASE(FRACT)
1196 NODE_NAME_CASE(FMAX)
1197 NODE_NAME_CASE(SMAX)
1198 NODE_NAME_CASE(UMAX)
1199 NODE_NAME_CASE(FMIN)
1200 NODE_NAME_CASE(SMIN)
1201 NODE_NAME_CASE(UMIN)
1202 NODE_NAME_CASE(BFE_U32)
1203 NODE_NAME_CASE(BFE_I32)
1206 NODE_NAME_CASE(URECIP)
1207 NODE_NAME_CASE(DOT4)
1208 NODE_NAME_CASE(EXPORT)
1209 NODE_NAME_CASE(CONST_ADDRESS)
1210 NODE_NAME_CASE(REGISTER_LOAD)
1211 NODE_NAME_CASE(REGISTER_STORE)
1212 NODE_NAME_CASE(LOAD_CONSTANT)
1213 NODE_NAME_CASE(LOAD_INPUT)
1214 NODE_NAME_CASE(SAMPLE)
1215 NODE_NAME_CASE(SAMPLEB)
1216 NODE_NAME_CASE(SAMPLED)
1217 NODE_NAME_CASE(SAMPLEL)
1218 NODE_NAME_CASE(STORE_MSKOR)
1219 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
1223 static void computeMaskedBitsForMinMax(const SDValue Op0,
1227 const SelectionDAG &DAG,
1229 APInt Op0Zero, Op0One;
1230 APInt Op1Zero, Op1One;
1231 DAG.ComputeMaskedBits(Op0, Op0Zero, Op0One, Depth);
1232 DAG.ComputeMaskedBits(Op1, Op1Zero, Op1One, Depth);
1234 KnownZero = Op0Zero & Op1Zero;
1235 KnownOne = Op0One & Op1One;
1238 void AMDGPUTargetLowering::computeMaskedBitsForTargetNode(
1242 const SelectionDAG &DAG,
1243 unsigned Depth) const {
1245 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
1246 unsigned Opc = Op.getOpcode();
1248 case ISD::INTRINSIC_WO_CHAIN: {
1249 // FIXME: The intrinsic should just use the node.
1250 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
1251 case AMDGPUIntrinsic::AMDGPU_imax:
1252 case AMDGPUIntrinsic::AMDGPU_umax:
1253 case AMDGPUIntrinsic::AMDGPU_imin:
1254 case AMDGPUIntrinsic::AMDGPU_umin:
1255 computeMaskedBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
1256 KnownZero, KnownOne, DAG, Depth);
1264 case AMDGPUISD::SMAX:
1265 case AMDGPUISD::UMAX:
1266 case AMDGPUISD::SMIN:
1267 case AMDGPUISD::UMIN:
1268 computeMaskedBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
1269 KnownZero, KnownOne, DAG, Depth);