1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "R600InstrInfo.h"
19 #include "SIDefines.h"
20 #include "SIISelLowering.h"
21 #include "SIMachineFunctionInfo.h"
22 #include "llvm/CodeGen/FunctionLoweringInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/IR/Function.h"
32 //===----------------------------------------------------------------------===//
33 // Instruction Selector Implementation
34 //===----------------------------------------------------------------------===//
37 /// AMDGPU specific code to select AMDGPU machine instructions for
38 /// SelectionDAG operations.
39 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
40 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
41 // make the right decision when generating code for different targets.
42 const AMDGPUSubtarget &Subtarget;
44 AMDGPUDAGToDAGISel(TargetMachine &TM);
45 virtual ~AMDGPUDAGToDAGISel();
47 SDNode *Select(SDNode *N) override;
48 const char *getPassName() const override;
49 void PostprocessISelDAG() override;
52 bool isInlineImmediate(SDNode *N) const;
53 inline SDValue getSmallIPtrImm(unsigned Imm);
54 bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
55 const R600InstrInfo *TII);
56 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
57 bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
59 // Complex pattern selectors
60 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
61 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
62 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
64 static bool checkType(const Value *ptr, unsigned int addrspace);
65 static bool checkPrivateAddress(const MachineMemOperand *Op);
67 static bool isGlobalStore(const StoreSDNode *N);
68 static bool isFlatStore(const StoreSDNode *N);
69 static bool isPrivateStore(const StoreSDNode *N);
70 static bool isLocalStore(const StoreSDNode *N);
71 static bool isRegionStore(const StoreSDNode *N);
73 bool isCPLoad(const LoadSDNode *N) const;
74 bool isConstantLoad(const LoadSDNode *N, int cbID) const;
75 bool isGlobalLoad(const LoadSDNode *N) const;
76 bool isFlatLoad(const LoadSDNode *N) const;
77 bool isParamLoad(const LoadSDNode *N) const;
78 bool isPrivateLoad(const LoadSDNode *N) const;
79 bool isLocalLoad(const LoadSDNode *N) const;
80 bool isRegionLoad(const LoadSDNode *N) const;
82 const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
83 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
84 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
86 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
87 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
88 bool isDSOffsetLegal(const SDValue &Base, unsigned Offset,
89 unsigned OffsetBits) const;
90 bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
91 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
92 SDValue &Offset1) const;
93 void SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
94 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
95 SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
97 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
98 SDValue &Offset) const;
99 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
100 SDValue &VAddr, SDValue &Offset,
102 bool SelectMUBUFScratch(SDValue Addr, SDValue &RSrc, SDValue &VAddr,
103 SDValue &SOffset, SDValue &ImmOffset) const;
104 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
105 SDValue &Offset, SDValue &GLC, SDValue &SLC,
107 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
108 SDValue &Offset, SDValue &GLC) const;
109 SDNode *SelectAddrSpaceCast(SDNode *N);
110 bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
111 bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
112 SDValue &Clamp, SDValue &Omod) const;
114 bool SelectVOP3Mods0Clamp(SDValue In, SDValue &Src, SDValue &SrcMods,
115 SDValue &Omod) const;
116 bool SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src, SDValue &SrcMods,
118 SDValue &Omod) const;
120 SDNode *SelectADD_SUB_I64(SDNode *N);
121 SDNode *SelectDIV_SCALE(SDNode *N);
123 // Include the pieces autogenerated from the target description.
124 #include "AMDGPUGenDAGISel.inc"
126 } // end anonymous namespace
128 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
129 // DAG, ready for instruction scheduling.
130 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM) {
131 return new AMDGPUDAGToDAGISel(TM);
134 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM)
135 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) {
138 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
141 bool AMDGPUDAGToDAGISel::isInlineImmediate(SDNode *N) const {
142 const SITargetLowering *TL
143 = static_cast<const SITargetLowering *>(getTargetLowering());
144 return TL->analyzeImmediate(N) == 0;
147 /// \brief Determine the register class for \p OpNo
148 /// \returns The register class of the virtual register that will be used for
149 /// the given operand number \OpNo or NULL if the register class cannot be
151 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
152 unsigned OpNo) const {
153 if (!N->isMachineOpcode())
156 switch (N->getMachineOpcode()) {
158 const MCInstrDesc &Desc =
159 TM.getSubtargetImpl()->getInstrInfo()->get(N->getMachineOpcode());
160 unsigned OpIdx = Desc.getNumDefs() + OpNo;
161 if (OpIdx >= Desc.getNumOperands())
163 int RegClass = Desc.OpInfo[OpIdx].RegClass;
167 return TM.getSubtargetImpl()->getRegisterInfo()->getRegClass(RegClass);
169 case AMDGPU::REG_SEQUENCE: {
170 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
171 const TargetRegisterClass *SuperRC =
172 TM.getSubtargetImpl()->getRegisterInfo()->getRegClass(RCID);
174 SDValue SubRegOp = N->getOperand(OpNo + 1);
175 unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
176 return TM.getSubtargetImpl()->getRegisterInfo()->getSubClassWithSubReg(
182 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
183 return CurDAG->getTargetConstant(Imm, MVT::i32);
186 bool AMDGPUDAGToDAGISel::SelectADDRParam(
187 SDValue Addr, SDValue& R1, SDValue& R2) {
189 if (Addr.getOpcode() == ISD::FrameIndex) {
190 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
191 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
192 R2 = CurDAG->getTargetConstant(0, MVT::i32);
195 R2 = CurDAG->getTargetConstant(0, MVT::i32);
197 } else if (Addr.getOpcode() == ISD::ADD) {
198 R1 = Addr.getOperand(0);
199 R2 = Addr.getOperand(1);
202 R2 = CurDAG->getTargetConstant(0, MVT::i32);
207 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
208 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
209 Addr.getOpcode() == ISD::TargetGlobalAddress) {
212 return SelectADDRParam(Addr, R1, R2);
216 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
217 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
218 Addr.getOpcode() == ISD::TargetGlobalAddress) {
222 if (Addr.getOpcode() == ISD::FrameIndex) {
223 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
224 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
225 R2 = CurDAG->getTargetConstant(0, MVT::i64);
228 R2 = CurDAG->getTargetConstant(0, MVT::i64);
230 } else if (Addr.getOpcode() == ISD::ADD) {
231 R1 = Addr.getOperand(0);
232 R2 = Addr.getOperand(1);
235 R2 = CurDAG->getTargetConstant(0, MVT::i64);
240 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
241 unsigned int Opc = N->getOpcode();
242 if (N->isMachineOpcode()) {
244 return nullptr; // Already selected.
247 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
250 // We are selecting i64 ADD here instead of custom lower it during
251 // DAG legalization, so we can fold some i64 ADDs used for address
252 // calculation into the LOAD and STORE instructions.
255 if (N->getValueType(0) != MVT::i64 ||
256 ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
259 return SelectADD_SUB_I64(N);
261 case ISD::SCALAR_TO_VECTOR:
262 case AMDGPUISD::BUILD_VERTICAL_VECTOR:
263 case ISD::BUILD_VECTOR: {
265 const AMDGPURegisterInfo *TRI = static_cast<const AMDGPURegisterInfo *>(
266 TM.getSubtargetImpl()->getRegisterInfo());
267 const SIRegisterInfo *SIRI = static_cast<const SIRegisterInfo *>(
268 TM.getSubtargetImpl()->getRegisterInfo());
269 EVT VT = N->getValueType(0);
270 unsigned NumVectorElts = VT.getVectorNumElements();
271 EVT EltVT = VT.getVectorElementType();
272 assert(EltVT.bitsEq(MVT::i32));
273 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
275 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
277 if (!U->isMachineOpcode()) {
280 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
284 if (SIRI->isSGPRClass(RC)) {
288 switch(NumVectorElts) {
289 case 1: RegClassID = UseVReg ? AMDGPU::VGPR_32RegClassID :
290 AMDGPU::SReg_32RegClassID;
292 case 2: RegClassID = UseVReg ? AMDGPU::VReg_64RegClassID :
293 AMDGPU::SReg_64RegClassID;
295 case 4: RegClassID = UseVReg ? AMDGPU::VReg_128RegClassID :
296 AMDGPU::SReg_128RegClassID;
298 case 8: RegClassID = UseVReg ? AMDGPU::VReg_256RegClassID :
299 AMDGPU::SReg_256RegClassID;
301 case 16: RegClassID = UseVReg ? AMDGPU::VReg_512RegClassID :
302 AMDGPU::SReg_512RegClassID;
304 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
307 // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
308 // that adds a 128 bits reg copy when going through TwoAddressInstructions
309 // pass. We want to avoid 128 bits copies as much as possible because they
310 // can't be bundled by our scheduler.
311 switch(NumVectorElts) {
312 case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
314 if (Opc == AMDGPUISD::BUILD_VERTICAL_VECTOR)
315 RegClassID = AMDGPU::R600_Reg128VerticalRegClassID;
317 RegClassID = AMDGPU::R600_Reg128RegClassID;
319 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
323 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, MVT::i32);
325 if (NumVectorElts == 1) {
326 return CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS, EltVT,
327 N->getOperand(0), RegClass);
330 assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not "
332 // 16 = Max Num Vector Elements
333 // 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
334 // 1 = Vector Register Class
335 SmallVector<SDValue, 16 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1);
337 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, MVT::i32);
338 bool IsRegSeq = true;
339 unsigned NOps = N->getNumOperands();
340 for (unsigned i = 0; i < NOps; i++) {
341 // XXX: Why is this here?
342 if (dyn_cast<RegisterSDNode>(N->getOperand(i))) {
346 RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
347 RegSeqArgs[1 + (2 * i) + 1] =
348 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
351 if (NOps != NumVectorElts) {
352 // Fill in the missing undef elements if this was a scalar_to_vector.
353 assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
355 MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
357 for (unsigned i = NOps; i < NumVectorElts; ++i) {
358 RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0);
359 RegSeqArgs[1 + (2 * i) + 1] =
360 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
366 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
369 case ISD::BUILD_PAIR: {
370 SDValue RC, SubReg0, SubReg1;
371 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
374 if (N->getValueType(0) == MVT::i128) {
375 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
376 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
377 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
378 } else if (N->getValueType(0) == MVT::i64) {
379 RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32);
380 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
381 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
383 llvm_unreachable("Unhandled value type for BUILD_PAIR");
385 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
386 N->getOperand(1), SubReg1 };
387 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
388 SDLoc(N), N->getValueType(0), Ops);
392 case ISD::ConstantFP: {
393 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
394 if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
395 N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N))
399 if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N))
400 Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue();
402 ConstantSDNode *C = cast<ConstantSDNode>(N);
403 Imm = C->getZExtValue();
406 SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
407 CurDAG->getConstant(Imm & 0xFFFFFFFF, MVT::i32));
408 SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
409 CurDAG->getConstant(Imm >> 32, MVT::i32));
410 const SDValue Ops[] = {
411 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
412 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
413 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32)
416 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, SDLoc(N),
417 N->getValueType(0), Ops);
420 case AMDGPUISD::REGISTER_LOAD: {
421 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
423 SDValue Addr, Offset;
425 SelectADDRIndirect(N->getOperand(1), Addr, Offset);
426 const SDValue Ops[] = {
429 CurDAG->getTargetConstant(0, MVT::i32),
432 return CurDAG->getMachineNode(AMDGPU::SI_RegisterLoad, SDLoc(N),
433 CurDAG->getVTList(MVT::i32, MVT::i64, MVT::Other),
436 case AMDGPUISD::REGISTER_STORE: {
437 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
439 SDValue Addr, Offset;
440 SelectADDRIndirect(N->getOperand(2), Addr, Offset);
441 const SDValue Ops[] = {
445 CurDAG->getTargetConstant(0, MVT::i32),
448 return CurDAG->getMachineNode(AMDGPU::SI_RegisterStorePseudo, SDLoc(N),
449 CurDAG->getVTList(MVT::Other),
453 case AMDGPUISD::BFE_I32:
454 case AMDGPUISD::BFE_U32: {
455 if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
458 // There is a scalar version available, but unlike the vector version which
459 // has a separate operand for the offset and width, the scalar version packs
460 // the width and offset into a single operand. Try to move to the scalar
461 // version if the offsets are constant, so that we can try to keep extended
462 // loads of kernel arguments in SGPRs.
464 // TODO: Technically we could try to pattern match scalar bitshifts of
465 // dynamic values, but it's probably not useful.
466 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
470 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
474 bool Signed = Opc == AMDGPUISD::BFE_I32;
476 // Transformation function, pack the offset and width of a BFE into
477 // the format expected by the S_BFE_I32 / S_BFE_U32. In the second
478 // source, bits [5:0] contain the offset and bits [22:16] the width.
480 uint32_t OffsetVal = Offset->getZExtValue();
481 uint32_t WidthVal = Width->getZExtValue();
483 uint32_t PackedVal = OffsetVal | WidthVal << 16;
485 SDValue PackedOffsetWidth = CurDAG->getTargetConstant(PackedVal, MVT::i32);
486 return CurDAG->getMachineNode(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32,
493 case AMDGPUISD::DIV_SCALE: {
494 return SelectDIV_SCALE(N);
496 case ISD::CopyToReg: {
497 const SITargetLowering& Lowering =
498 *static_cast<const SITargetLowering*>(getTargetLowering());
499 Lowering.legalizeTargetIndependentNode(N, *CurDAG);
502 case ISD::ADDRSPACECAST:
503 return SelectAddrSpaceCast(N);
506 return SelectCode(N);
510 bool AMDGPUDAGToDAGISel::checkType(const Value *Ptr, unsigned AS) {
511 assert(AS != 0 && "Use checkPrivateAddress instead.");
515 return Ptr->getType()->getPointerAddressSpace() == AS;
518 bool AMDGPUDAGToDAGISel::checkPrivateAddress(const MachineMemOperand *Op) {
519 if (Op->getPseudoValue())
522 if (PointerType *PT = dyn_cast<PointerType>(Op->getValue()->getType()))
523 return PT->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
528 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
529 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
532 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
533 const Value *MemVal = N->getMemOperand()->getValue();
534 return (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
535 !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
536 !checkType(MemVal, AMDGPUAS::REGION_ADDRESS));
539 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
540 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
543 bool AMDGPUDAGToDAGISel::isFlatStore(const StoreSDNode *N) {
544 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::FLAT_ADDRESS);
547 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
548 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
551 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int CbId) const {
552 const Value *MemVal = N->getMemOperand()->getValue();
554 return checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS);
556 return checkType(MemVal, AMDGPUAS::CONSTANT_BUFFER_0 + CbId);
559 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const {
560 if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS) {
561 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
562 if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
563 N->getMemoryVT().bitsLT(MVT::i32)) {
567 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
570 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) const {
571 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::PARAM_I_ADDRESS);
574 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) const {
575 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
578 bool AMDGPUDAGToDAGISel::isFlatLoad(const LoadSDNode *N) const {
579 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::FLAT_ADDRESS);
582 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) const {
583 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
586 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) const {
587 MachineMemOperand *MMO = N->getMemOperand();
588 if (checkPrivateAddress(N->getMemOperand())) {
590 const PseudoSourceValue *PSV = MMO->getPseudoValue();
591 if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
599 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const {
600 if (checkPrivateAddress(N->getMemOperand())) {
601 // Check to make sure we are not a constant pool load or a constant load
602 // that is marked as a private load
603 if (isCPLoad(N) || isConstantLoad(N, -1)) {
608 const Value *MemVal = N->getMemOperand()->getValue();
609 if (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
610 !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
611 !checkType(MemVal, AMDGPUAS::FLAT_ADDRESS) &&
612 !checkType(MemVal, AMDGPUAS::REGION_ADDRESS) &&
613 !checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS) &&
614 !checkType(MemVal, AMDGPUAS::PARAM_D_ADDRESS) &&
615 !checkType(MemVal, AMDGPUAS::PARAM_I_ADDRESS)) {
621 const char *AMDGPUDAGToDAGISel::getPassName() const {
622 return "AMDGPU DAG->DAG Pattern Instruction Selection";
630 //===----------------------------------------------------------------------===//
632 //===----------------------------------------------------------------------===//
634 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
636 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
637 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
643 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
644 SDValue& BaseReg, SDValue &Offset) {
645 if (!isa<ConstantSDNode>(Addr)) {
647 Offset = CurDAG->getIntPtrConstant(0, true);
653 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
655 ConstantSDNode *IMMOffset;
657 if (Addr.getOpcode() == ISD::ADD
658 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
659 && isInt<16>(IMMOffset->getZExtValue())) {
661 Base = Addr.getOperand(0);
662 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
664 // If the pointer address is constant, we can move it to the offset field.
665 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
666 && isInt<16>(IMMOffset->getZExtValue())) {
667 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
668 SDLoc(CurDAG->getEntryNode()),
669 AMDGPU::ZERO, MVT::i32);
670 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
674 // Default case, no offset
676 Offset = CurDAG->getTargetConstant(0, MVT::i32);
680 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
684 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
685 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
686 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
687 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
688 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
689 Base = Addr.getOperand(0);
690 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
693 Offset = CurDAG->getTargetConstant(0, MVT::i32);
699 SDNode *AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
701 SDValue LHS = N->getOperand(0);
702 SDValue RHS = N->getOperand(1);
704 bool IsAdd = (N->getOpcode() == ISD::ADD);
706 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
707 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
709 SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
710 DL, MVT::i32, LHS, Sub0);
711 SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
712 DL, MVT::i32, LHS, Sub1);
714 SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
715 DL, MVT::i32, RHS, Sub0);
716 SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
717 DL, MVT::i32, RHS, Sub1);
719 SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
720 SDValue AddLoArgs[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) };
723 unsigned Opc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
724 unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
726 SDNode *AddLo = CurDAG->getMachineNode( Opc, DL, VTList, AddLoArgs);
727 SDValue Carry(AddLo, 1);
729 = CurDAG->getMachineNode(CarryOpc, DL, MVT::i32,
730 SDValue(Hi0, 0), SDValue(Hi1, 0), Carry);
733 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
739 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args);
742 SDNode *AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
744 EVT VT = N->getValueType(0);
746 assert(VT == MVT::f32 || VT == MVT::f64);
749 = (VT == MVT::f64) ? AMDGPU::V_DIV_SCALE_F64 : AMDGPU::V_DIV_SCALE_F32;
751 const SDValue Zero = CurDAG->getTargetConstant(0, MVT::i32);
752 const SDValue False = CurDAG->getTargetConstant(0, MVT::i1);
754 Zero, // src0_modifiers
755 N->getOperand(0), // src0
756 Zero, // src1_modifiers
757 N->getOperand(1), // src1
758 Zero, // src2_modifiers
759 N->getOperand(2), // src2
764 return CurDAG->SelectNodeTo(N, Opc, VT, MVT::i1, Ops);
767 bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset,
768 unsigned OffsetBits) const {
769 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
770 if ((OffsetBits == 16 && !isUInt<16>(Offset)) ||
771 (OffsetBits == 8 && !isUInt<8>(Offset)))
774 if (ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
777 // On Southern Islands instruction with a negative base value and an offset
778 // don't seem to work.
779 return CurDAG->SignBitIsZero(Base);
782 bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
783 SDValue &Offset) const {
784 if (CurDAG->isBaseWithConstantOffset(Addr)) {
785 SDValue N0 = Addr.getOperand(0);
786 SDValue N1 = Addr.getOperand(1);
787 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
788 if (isDSOffsetLegal(N0, C1->getSExtValue(), 16)) {
796 // If we have a constant address, prefer to put the constant into the
797 // offset. This can save moves to load the constant address since multiple
798 // operations can share the zero base address register, and enables merging
799 // into read2 / write2 instructions.
800 if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
801 if (isUInt<16>(CAddr->getZExtValue())) {
802 SDValue Zero = CurDAG->getTargetConstant(0, MVT::i32);
803 MachineSDNode *MovZero = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
804 SDLoc(Addr), MVT::i32, Zero);
805 Base = SDValue(MovZero, 0);
813 Offset = CurDAG->getTargetConstant(0, MVT::i16);
817 bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
819 SDValue &Offset1) const {
820 if (CurDAG->isBaseWithConstantOffset(Addr)) {
821 SDValue N0 = Addr.getOperand(0);
822 SDValue N1 = Addr.getOperand(1);
823 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
824 unsigned DWordOffset0 = C1->getZExtValue() / 4;
825 unsigned DWordOffset1 = DWordOffset0 + 1;
827 if (isDSOffsetLegal(N0, DWordOffset1, 8)) {
829 Offset0 = CurDAG->getTargetConstant(DWordOffset0, MVT::i8);
830 Offset1 = CurDAG->getTargetConstant(DWordOffset1, MVT::i8);
835 if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
836 unsigned DWordOffset0 = CAddr->getZExtValue() / 4;
837 unsigned DWordOffset1 = DWordOffset0 + 1;
838 assert(4 * DWordOffset0 == CAddr->getZExtValue());
840 if (isUInt<8>(DWordOffset0) && isUInt<8>(DWordOffset1)) {
841 SDValue Zero = CurDAG->getTargetConstant(0, MVT::i32);
842 MachineSDNode *MovZero
843 = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
844 SDLoc(Addr), MVT::i32, Zero);
845 Base = SDValue(MovZero, 0);
846 Offset0 = CurDAG->getTargetConstant(DWordOffset0, MVT::i8);
847 Offset1 = CurDAG->getTargetConstant(DWordOffset1, MVT::i8);
854 Offset0 = CurDAG->getTargetConstant(0, MVT::i8);
855 Offset1 = CurDAG->getTargetConstant(1, MVT::i8);
859 static bool isLegalMUBUFImmOffset(const ConstantSDNode *Imm) {
860 return isUInt<12>(Imm->getZExtValue());
863 void AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
864 SDValue &VAddr, SDValue &SOffset,
865 SDValue &Offset, SDValue &Offen,
866 SDValue &Idxen, SDValue &Addr64,
867 SDValue &GLC, SDValue &SLC,
868 SDValue &TFE) const {
871 GLC = CurDAG->getTargetConstant(0, MVT::i1);
872 SLC = CurDAG->getTargetConstant(0, MVT::i1);
873 TFE = CurDAG->getTargetConstant(0, MVT::i1);
875 Idxen = CurDAG->getTargetConstant(0, MVT::i1);
876 Offen = CurDAG->getTargetConstant(0, MVT::i1);
877 Addr64 = CurDAG->getTargetConstant(0, MVT::i1);
878 SOffset = CurDAG->getTargetConstant(0, MVT::i32);
880 if (CurDAG->isBaseWithConstantOffset(Addr)) {
881 SDValue N0 = Addr.getOperand(0);
882 SDValue N1 = Addr.getOperand(1);
883 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
885 if (isLegalMUBUFImmOffset(C1)) {
887 if (N0.getOpcode() == ISD::ADD) {
888 // (add (add N2, N3), C1) -> addr64
889 SDValue N2 = N0.getOperand(0);
890 SDValue N3 = N0.getOperand(1);
891 Addr64 = CurDAG->getTargetConstant(1, MVT::i1);
894 Offset = CurDAG->getTargetConstant(C1->getZExtValue(), MVT::i16);
898 // (add N0, C1) -> offset
899 VAddr = CurDAG->getTargetConstant(0, MVT::i32);
901 Offset = CurDAG->getTargetConstant(C1->getZExtValue(), MVT::i16);
905 if (Addr.getOpcode() == ISD::ADD) {
906 // (add N0, N1) -> addr64
907 SDValue N0 = Addr.getOperand(0);
908 SDValue N1 = Addr.getOperand(1);
909 Addr64 = CurDAG->getTargetConstant(1, MVT::i1);
912 Offset = CurDAG->getTargetConstant(0, MVT::i16);
916 // default case -> offset
917 VAddr = CurDAG->getTargetConstant(0, MVT::i32);
919 Offset = CurDAG->getTargetConstant(0, MVT::i16);
923 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
925 SDValue &Offset) const {
926 SDValue Ptr, SOffset, Offen, Idxen, Addr64, GLC, SLC, TFE;
928 SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
931 ConstantSDNode *C = cast<ConstantSDNode>(Addr64);
932 if (C->getSExtValue()) {
935 const SITargetLowering& Lowering =
936 *static_cast<const SITargetLowering*>(getTargetLowering());
938 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0);
945 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
946 SDValue &VAddr, SDValue &Offset,
947 SDValue &SLC) const {
948 SLC = CurDAG->getTargetConstant(0, MVT::i1);
950 return SelectMUBUFAddr64(Addr, SRsrc, VAddr, Offset);
953 bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
954 SDValue &VAddr, SDValue &SOffset,
955 SDValue &ImmOffset) const {
958 MachineFunction &MF = CurDAG->getMachineFunction();
959 const SIRegisterInfo *TRI =
960 static_cast<const SIRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
961 MachineRegisterInfo &MRI = MF.getRegInfo();
962 const SITargetLowering& Lowering =
963 *static_cast<const SITargetLowering*>(getTargetLowering());
965 unsigned ScratchPtrReg =
966 TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_PTR);
967 unsigned ScratchOffsetReg =
968 TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET);
969 Lowering.CreateLiveInRegister(*CurDAG, &AMDGPU::SReg_32RegClass,
970 ScratchOffsetReg, MVT::i32);
973 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
974 MRI.getLiveInVirtReg(ScratchPtrReg), MVT::i64);
975 Rsrc = SDValue(Lowering.buildScratchRSRC(*CurDAG, DL, ScratchPtr), 0);
976 SOffset = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
977 MRI.getLiveInVirtReg(ScratchOffsetReg), MVT::i32);
980 if (CurDAG->isBaseWithConstantOffset(Addr)) {
981 SDValue N1 = Addr.getOperand(1);
982 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
984 if (isLegalMUBUFImmOffset(C1)) {
985 VAddr = Addr.getOperand(0);
986 ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), MVT::i16);
992 if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
993 isa<FrameIndexSDNode>(Addr.getOperand(0))) {
994 VAddr = Addr.getOperand(1);
995 ImmOffset = Addr.getOperand(0);
1000 if (isa<FrameIndexSDNode>(Addr)) {
1001 VAddr = SDValue(CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32, DL, MVT::i32,
1002 CurDAG->getConstant(0, MVT::i32)), 0);
1009 ImmOffset = CurDAG->getTargetConstant(0, MVT::i16);
1013 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1014 SDValue &SOffset, SDValue &Offset,
1015 SDValue &GLC, SDValue &SLC,
1016 SDValue &TFE) const {
1017 SDValue Ptr, VAddr, Offen, Idxen, Addr64;
1018 const SIInstrInfo *TII =
1019 static_cast<const SIInstrInfo *>(Subtarget.getInstrInfo());
1021 SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
1024 if (!cast<ConstantSDNode>(Offen)->getSExtValue() &&
1025 !cast<ConstantSDNode>(Idxen)->getSExtValue() &&
1026 !cast<ConstantSDNode>(Addr64)->getSExtValue()) {
1027 uint64_t Rsrc = TII->getDefaultRsrcDataFormat() |
1028 APInt::getAllOnesValue(32).getZExtValue(); // Size
1031 const SITargetLowering& Lowering =
1032 *static_cast<const SITargetLowering*>(getTargetLowering());
1034 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0);
1040 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1041 SDValue &Soffset, SDValue &Offset,
1042 SDValue &GLC) const {
1045 return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
1048 // FIXME: This is incorrect and only enough to be able to compile.
1049 SDNode *AMDGPUDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
1050 AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(N);
1053 assert(Subtarget.hasFlatAddressSpace() &&
1054 "addrspacecast only supported with flat address space!");
1056 assert((ASC->getSrcAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS &&
1057 ASC->getDestAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS) &&
1058 "Cannot cast address space to / from constant address!");
1060 assert((ASC->getSrcAddressSpace() == AMDGPUAS::FLAT_ADDRESS ||
1061 ASC->getDestAddressSpace() == AMDGPUAS::FLAT_ADDRESS) &&
1062 "Can only cast to / from flat address space!");
1064 // The flat instructions read the address as the index of the VGPR holding the
1065 // address, so casting should just be reinterpreting the base VGPR, so just
1066 // insert trunc / bitcast / zext.
1068 SDValue Src = ASC->getOperand(0);
1069 EVT DestVT = ASC->getValueType(0);
1070 EVT SrcVT = Src.getValueType();
1072 unsigned SrcSize = SrcVT.getSizeInBits();
1073 unsigned DestSize = DestVT.getSizeInBits();
1075 if (SrcSize > DestSize) {
1076 assert(SrcSize == 64 && DestSize == 32);
1077 return CurDAG->getMachineNode(
1078 TargetOpcode::EXTRACT_SUBREG,
1082 CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32));
1086 if (DestSize > SrcSize) {
1087 assert(SrcSize == 32 && DestSize == 64);
1089 SDValue RC = CurDAG->getTargetConstant(AMDGPU::VSrc_64RegClassID, MVT::i32);
1091 const SDValue Ops[] = {
1094 CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
1095 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
1096 CurDAG->getConstant(0, MVT::i32)), 0),
1097 CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32)
1100 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
1101 SDLoc(N), N->getValueType(0), Ops);
1104 assert(SrcSize == 64 && DestSize == 64);
1105 return CurDAG->getNode(ISD::BITCAST, DL, DestVT, Src).getNode();
1108 bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
1109 SDValue &SrcMods) const {
1115 if (Src.getOpcode() == ISD::FNEG) {
1116 Mods |= SISrcMods::NEG;
1117 Src = Src.getOperand(0);
1120 if (Src.getOpcode() == ISD::FABS) {
1121 Mods |= SISrcMods::ABS;
1122 Src = Src.getOperand(0);
1125 SrcMods = CurDAG->getTargetConstant(Mods, MVT::i32);
1130 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
1131 SDValue &SrcMods, SDValue &Clamp,
1132 SDValue &Omod) const {
1133 // FIXME: Handle Clamp and Omod
1134 Clamp = CurDAG->getTargetConstant(0, MVT::i32);
1135 Omod = CurDAG->getTargetConstant(0, MVT::i32);
1137 return SelectVOP3Mods(In, Src, SrcMods);
1140 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp(SDValue In, SDValue &Src,
1142 SDValue &Omod) const {
1143 // FIXME: Handle Omod
1144 Omod = CurDAG->getTargetConstant(0, MVT::i32);
1146 return SelectVOP3Mods(In, Src, SrcMods);
1149 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src,
1152 SDValue &Omod) const {
1153 Clamp = Omod = CurDAG->getTargetConstant(0, MVT::i32);
1154 return SelectVOP3Mods(In, Src, SrcMods);
1157 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
1158 const AMDGPUTargetLowering& Lowering =
1159 *static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
1160 bool IsModified = false;
1163 // Go over all selected nodes and try to fold them a bit more
1164 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
1165 E = CurDAG->allnodes_end(); I != E; ++I) {
1169 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
1173 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
1174 if (ResNode != Node) {
1175 ReplaceUses(Node, ResNode);
1179 CurDAG->RemoveDeadNodes();
1180 } while (IsModified);