1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code. When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
16 //===----------------------------------------------------------------------===//
19 #include "AMDGPUAsmPrinter.h"
21 #include "AMDKernelCodeT.h"
22 #include "AMDGPUSubtarget.h"
23 #include "R600Defines.h"
24 #include "R600MachineFunctionInfo.h"
25 #include "R600RegisterInfo.h"
26 #include "SIDefines.h"
27 #include "SIMachineFunctionInfo.h"
28 #include "SIRegisterInfo.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/MC/MCContext.h"
31 #include "llvm/MC/MCSectionELF.h"
32 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/Support/ELF.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/TargetRegistry.h"
36 #include "llvm/Target/TargetLoweringObjectFile.h"
40 // TODO: This should get the default rounding mode from the kernel. We just set
41 // the default here, but this could change if the OpenCL rounding mode pragmas
44 // The denormal mode here should match what is reported by the OpenCL runtime
45 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
46 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
48 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
49 // precision, and leaves single precision to flush all and does not report
50 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
51 // CL_FP_DENORM for both.
53 // FIXME: It seems some instructions do not support single precision denormals
54 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
55 // and sin_f32, cos_f32 on most parts).
57 // We want to use these instructions, and using fp32 denormals also causes
58 // instructions to run at the double precision rate for the device so it's
59 // probably best to just report no single precision denormals.
60 static uint32_t getFPMode(const MachineFunction &F) {
61 const AMDGPUSubtarget& ST = F.getSubtarget<AMDGPUSubtarget>();
62 // TODO: Is there any real use for the flush in only / flush out only modes?
64 uint32_t FP32Denormals =
65 ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
67 uint32_t FP64Denormals =
68 ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
70 return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
71 FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
72 FP_DENORM_MODE_SP(FP32Denormals) |
73 FP_DENORM_MODE_DP(FP64Denormals);
77 createAMDGPUAsmPrinterPass(TargetMachine &tm,
78 std::unique_ptr<MCStreamer> &&Streamer) {
79 return new AMDGPUAsmPrinter(tm, std::move(Streamer));
82 extern "C" void LLVMInitializeR600AsmPrinter() {
83 TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
84 TargetRegistry::RegisterAsmPrinter(TheGCNTarget, createAMDGPUAsmPrinterPass);
87 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
88 std::unique_ptr<MCStreamer> Streamer)
89 : AsmPrinter(TM, std::move(Streamer)) {}
91 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
93 // This label is used to mark the end of the .text section.
94 const TargetLoweringObjectFile &TLOF = getObjFileLowering();
95 OutStreamer.SwitchSection(TLOF.getTextSection());
96 MCSymbol *EndOfTextLabel =
97 OutContext.GetOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
98 OutStreamer.EmitLabel(EndOfTextLabel);
101 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
103 // The starting address of all shader programs must be 256 bytes aligned.
106 SetupMachineFunction(MF);
108 EmitFunctionHeader();
110 MCContext &Context = getObjFileLowering().getContext();
111 const MCSectionELF *ConfigSection =
112 Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
113 OutStreamer.SwitchSection(ConfigSection);
115 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
116 SIProgramInfo KernelInfo;
117 if (STM.isAmdHsaOS()) {
118 getSIProgramInfo(KernelInfo, MF);
119 EmitAmdKernelCodeT(MF, KernelInfo);
120 OutStreamer.EmitCodeAlignment(2 << (MF.getAlignment() - 1));
121 } else if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
122 getSIProgramInfo(KernelInfo, MF);
123 EmitProgramInfoSI(MF, KernelInfo);
125 EmitProgramInfoR600(MF);
130 DisasmLineMaxLen = 0;
132 OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
136 const MCSectionELF *CommentSection =
137 Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
138 OutStreamer.SwitchSection(CommentSection);
140 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
141 OutStreamer.emitRawComment(" Kernel info:", false);
142 OutStreamer.emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
144 OutStreamer.emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
146 OutStreamer.emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
148 OutStreamer.emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
150 OutStreamer.emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
152 OutStreamer.emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
155 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
156 OutStreamer.emitRawComment(
157 Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
161 if (STM.dumpCode()) {
163 OutStreamer.SwitchSection(
164 Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
166 for (size_t i = 0; i < DisasmLines.size(); ++i) {
167 std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
168 Comment += " ; " + HexLines[i] + "\n";
170 OutStreamer.EmitBytes(StringRef(DisasmLines[i]));
171 OutStreamer.EmitBytes(StringRef(Comment));
178 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
180 bool killPixel = false;
181 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
182 const R600RegisterInfo *RI =
183 static_cast<const R600RegisterInfo *>(STM.getRegisterInfo());
184 const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
186 for (const MachineBasicBlock &MBB : MF) {
187 for (const MachineInstr &MI : MBB) {
188 if (MI.getOpcode() == AMDGPU::KILLGT)
190 unsigned numOperands = MI.getNumOperands();
191 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
192 const MachineOperand &MO = MI.getOperand(op_idx);
195 unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
197 // Register with value > 127 aren't GPR
200 MaxGPR = std::max(MaxGPR, HWReg);
206 if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
207 // Evergreen / Northern Islands
208 switch (MFI->getShaderType()) {
209 default: // Fall through
210 case ShaderType::COMPUTE: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
211 case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
212 case ShaderType::PIXEL: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
213 case ShaderType::VERTEX: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
217 switch (MFI->getShaderType()) {
218 default: // Fall through
219 case ShaderType::GEOMETRY: // Fall through
220 case ShaderType::COMPUTE: // Fall through
221 case ShaderType::VERTEX: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
222 case ShaderType::PIXEL: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
226 OutStreamer.EmitIntValue(RsrcReg, 4);
227 OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
228 S_STACK_SIZE(MFI->StackSize), 4);
229 OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
230 OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
232 if (MFI->getShaderType() == ShaderType::COMPUTE) {
233 OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
234 OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
238 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
239 const MachineFunction &MF) const {
240 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
241 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
242 uint64_t CodeSize = 0;
243 unsigned MaxSGPR = 0;
244 unsigned MaxVGPR = 0;
245 bool VCCUsed = false;
246 bool FlatUsed = false;
247 const SIRegisterInfo *RI =
248 static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
250 for (const MachineBasicBlock &MBB : MF) {
251 for (const MachineInstr &MI : MBB) {
252 // TODO: CodeSize should account for multiple functions.
253 CodeSize += MI.getDesc().Size;
255 unsigned numOperands = MI.getNumOperands();
256 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
257 const MachineOperand &MO = MI.getOperand(op_idx);
264 unsigned reg = MO.getReg();
265 if (reg == AMDGPU::VCC || reg == AMDGPU::VCC_LO ||
266 reg == AMDGPU::VCC_HI) {
269 } else if (reg == AMDGPU::FLAT_SCR ||
270 reg == AMDGPU::FLAT_SCR_LO ||
271 reg == AMDGPU::FLAT_SCR_HI) {
284 if (AMDGPU::SReg_32RegClass.contains(reg)) {
287 } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
290 } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
293 } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
296 } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
299 } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
302 } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
305 } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
308 } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
311 } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
314 } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
318 llvm_unreachable("Unknown register class");
320 unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
321 unsigned maxUsed = hwReg + width - 1;
323 MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
325 MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
337 // We found the maximum register index. They start at 0, so add one to get the
338 // number of registers.
339 ProgInfo.NumVGPR = MaxVGPR + 1;
340 ProgInfo.NumSGPR = MaxSGPR + 1;
342 ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
343 ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
344 // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
346 ProgInfo.FloatMode = getFPMode(MF);
348 // XXX: Not quite sure what this does, but sc seems to unset this.
349 ProgInfo.IEEEMode = 0;
351 // Do not clamp NAN to 0.
352 ProgInfo.DX10Clamp = 0;
354 const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
355 ProgInfo.ScratchSize = FrameInfo->estimateStackSize(MF);
357 ProgInfo.FlatUsed = FlatUsed;
358 ProgInfo.VCCUsed = VCCUsed;
359 ProgInfo.CodeLen = CodeSize;
361 unsigned LDSAlignShift;
362 if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
363 // LDS is allocated in 64 dword blocks.
366 // LDS is allocated in 128 dword blocks.
370 unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
371 MFI->getMaximumWorkGroupSize(MF);
373 ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;
375 RoundUpToAlignment(ProgInfo.LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
377 // Scratch is allocated in 256 dword blocks.
378 unsigned ScratchAlignShift = 10;
379 // We need to program the hardware with the amount of scratch memory that
380 // is used by the entire wave. ProgInfo.ScratchSize is the amount of
381 // scratch memory used per thread.
382 ProgInfo.ScratchBlocks =
383 RoundUpToAlignment(ProgInfo.ScratchSize * STM.getWavefrontSize(),
384 1 << ScratchAlignShift) >> ScratchAlignShift;
386 ProgInfo.ComputePGMRSrc1 =
387 S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
388 S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
389 S_00B848_PRIORITY(ProgInfo.Priority) |
390 S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
391 S_00B848_PRIV(ProgInfo.Priv) |
392 S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
393 S_00B848_IEEE_MODE(ProgInfo.DebugMode) |
394 S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
396 ProgInfo.ComputePGMRSrc2 =
397 S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
398 S_00B84C_USER_SGPR(MFI->NumUserSGPRs) |
399 S_00B84C_TGID_X_EN(1) |
400 S_00B84C_TGID_Y_EN(1) |
401 S_00B84C_TGID_Z_EN(1) |
402 S_00B84C_TG_SIZE_EN(1) |
403 S_00B84C_TIDIG_COMP_CNT(2) |
404 S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks);
407 static unsigned getRsrcReg(unsigned ShaderType) {
408 switch (ShaderType) {
409 default: // Fall through
410 case ShaderType::COMPUTE: return R_00B848_COMPUTE_PGM_RSRC1;
411 case ShaderType::GEOMETRY: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
412 case ShaderType::PIXEL: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
413 case ShaderType::VERTEX: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
417 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
418 const SIProgramInfo &KernelInfo) {
419 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
420 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
421 unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
423 if (MFI->getShaderType() == ShaderType::COMPUTE) {
424 OutStreamer.EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
426 OutStreamer.EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
428 OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
429 OutStreamer.EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
431 OutStreamer.EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
432 OutStreamer.EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
434 // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
435 // 0" comment but I don't see a corresponding field in the register spec.
437 OutStreamer.EmitIntValue(RsrcReg, 4);
438 OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
439 S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
440 if (STM.isVGPRSpillingEnabled(MFI)) {
441 OutStreamer.EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
442 OutStreamer.EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
446 if (MFI->getShaderType() == ShaderType::PIXEL) {
447 OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
448 OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
449 OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
450 OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);
454 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
455 const SIProgramInfo &KernelInfo) const {
456 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
457 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
458 amd_kernel_code_t header;
460 memset(&header, 0, sizeof(header));
462 header.amd_code_version_major = AMD_CODE_VERSION_MAJOR;
463 header.amd_code_version_minor = AMD_CODE_VERSION_MINOR;
465 header.struct_byte_size = sizeof(amd_kernel_code_t);
467 header.target_chip = STM.getAmdKernelCodeChipID();
469 header.kernel_code_entry_byte_offset = (1ULL << MF.getAlignment());
471 header.compute_pgm_resource_registers =
472 KernelInfo.ComputePGMRSrc1 |
473 (KernelInfo.ComputePGMRSrc2 << 32);
476 header.code_properties = AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR |
477 AMD_CODE_PROPERTY_IS_PTR64;
479 if (KernelInfo.FlatUsed)
480 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
482 if (KernelInfo.ScratchBlocks)
483 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE;
485 header.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
486 header.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
488 // MFI->ABIArgOffset is the number of bytes for the kernel arguments
489 // plus 36. 36 is the number of bytes reserved at the begining of the
490 // input buffer to store work-group size information.
491 // FIXME: We should be adding the size of the implicit arguments
493 header.kernarg_segment_byte_size = MFI->ABIArgOffset;
495 header.wavefront_sgpr_count = KernelInfo.NumSGPR;
496 header.workitem_vgpr_count = KernelInfo.NumVGPR;
498 // FIXME: What values do I put for these alignments
499 header.kernarg_segment_alignment = 0;
500 header.group_segment_alignment = 0;
501 header.private_segment_alignment = 0;
503 header.code_type = 1; // HSA_EXT_CODE_KERNEL
505 header.wavefront_size = STM.getWavefrontSize();
507 const MCSectionELF *VersionSection =
508 OutContext.getELFSection(".hsa.version", ELF::SHT_PROGBITS, 0);
509 OutStreamer.SwitchSection(VersionSection);
510 OutStreamer.EmitBytes(Twine("HSA Code Unit:" +
511 Twine(header.hsail_version_major) + "." +
512 Twine(header.hsail_version_minor) + ":" +
514 Twine(header.amd_code_version_major) + "." +
515 Twine(header.amd_code_version_minor) + ":" +
518 OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
521 OutStreamer.emitRawComment("amd_code_version_major = " +
522 Twine(header.amd_code_version_major), false);
523 OutStreamer.emitRawComment("amd_code_version_minor = " +
524 Twine(header.amd_code_version_minor), false);
525 OutStreamer.emitRawComment("struct_byte_size = " +
526 Twine(header.struct_byte_size), false);
527 OutStreamer.emitRawComment("target_chip = " +
528 Twine(header.target_chip), false);
529 OutStreamer.emitRawComment(" compute_pgm_rsrc1: " +
530 Twine::utohexstr(KernelInfo.ComputePGMRSrc1), false);
531 OutStreamer.emitRawComment(" compute_pgm_rsrc2: " +
532 Twine::utohexstr(KernelInfo.ComputePGMRSrc2), false);
533 OutStreamer.emitRawComment("enable_sgpr_private_segment_buffer = " +
534 Twine((bool)(header.code_properties &
535 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE)), false);
536 OutStreamer.emitRawComment("enable_sgpr_kernarg_segment_ptr = " +
537 Twine((bool)(header.code_properties &
538 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)), false);
539 OutStreamer.emitRawComment("private_element_size = 2 ", false);
540 OutStreamer.emitRawComment("is_ptr64 = " +
541 Twine((bool)(header.code_properties & AMD_CODE_PROPERTY_IS_PTR64)), false);
542 OutStreamer.emitRawComment("workitem_private_segment_byte_size = " +
543 Twine(header.workitem_private_segment_byte_size),
545 OutStreamer.emitRawComment("workgroup_group_segment_byte_size = " +
546 Twine(header.workgroup_group_segment_byte_size),
548 OutStreamer.emitRawComment("gds_segment_byte_size = " +
549 Twine(header.gds_segment_byte_size), false);
550 OutStreamer.emitRawComment("kernarg_segment_byte_size = " +
551 Twine(header.kernarg_segment_byte_size), false);
552 OutStreamer.emitRawComment("wavefront_sgpr_count = " +
553 Twine(header.wavefront_sgpr_count), false);
554 OutStreamer.emitRawComment("workitem_vgpr_count = " +
555 Twine(header.workitem_vgpr_count), false);
556 OutStreamer.emitRawComment("code_type = " + Twine(header.code_type), false);
557 OutStreamer.emitRawComment("wavefront_size = " +
558 Twine((int)header.wavefront_size), false);
559 OutStreamer.emitRawComment("optimization_level = " +
560 Twine(header.optimization_level), false);
561 OutStreamer.emitRawComment("hsail_profile = " +
562 Twine(header.hsail_profile), false);
563 OutStreamer.emitRawComment("hsail_machine_model = " +
564 Twine(header.hsail_machine_model), false);
565 OutStreamer.emitRawComment("hsail_version_major = " +
566 Twine(header.hsail_version_major), false);
567 OutStreamer.emitRawComment("hsail_version_minor = " +
568 Twine(header.hsail_version_minor), false);
571 OutStreamer.EmitBytes(StringRef((char*)&header, sizeof(header)));