lib/Target/R600/AMDGPUAsmPrinter.cpp

   1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 ///
  12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
  13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
  14 /// an MCObjectStreamer it outputs binary code.
  15 //
  16 //===----------------------------------------------------------------------===//
  17 //
  18
  19 #include "AMDGPUAsmPrinter.h"
  20 #include "AMDGPU.h"
  21 #include "AMDKernelCodeT.h"
  22 #include "AMDGPUSubtarget.h"
  23 #include "R600Defines.h"
  24 #include "R600MachineFunctionInfo.h"
  25 #include "R600RegisterInfo.h"
  26 #include "SIDefines.h"
  27 #include "SIMachineFunctionInfo.h"
  28 #include "SIRegisterInfo.h"
  29 #include "llvm/CodeGen/MachineFrameInfo.h"
  30 #include "llvm/MC/MCContext.h"
  31 #include "llvm/MC/MCSectionELF.h"
  32 #include "llvm/MC/MCStreamer.h"
  33 #include "llvm/Support/ELF.h"
  34 #include "llvm/Support/MathExtras.h"
  35 #include "llvm/Support/TargetRegistry.h"
  36 #include "llvm/Target/TargetLoweringObjectFile.h"
  37
  38 using namespace llvm;
  39
  40 // TODO: This should get the default rounding mode from the kernel. We just set
  41 // the default here, but this could change if the OpenCL rounding mode pragmas
  42 // are used.
  43 //
  44 // The denormal mode here should match what is reported by the OpenCL runtime
  45 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
  46 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
  47 //
  48 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
  49 // precision, and leaves single precision to flush all and does not report
  50 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
  51 // CL_FP_DENORM for both.
  52 //
  53 // FIXME: It seems some instructions do not support single precision denormals
  54 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
  55 // and sin_f32, cos_f32 on most parts).
  56
  57 // We want to use these instructions, and using fp32 denormals also causes
  58 // instructions to run at the double precision rate for the device so it's
  59 // probably best to just report no single precision denormals.
  60 static uint32_t getFPMode(const MachineFunction &F) {
  61   const AMDGPUSubtarget& ST = F.getTarget().getSubtarget<AMDGPUSubtarget>();
  62   // TODO: Is there any real use for the flush in only / flush out only modes?
  63
  64   uint32_t FP32Denormals =
  65     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
  66
  67   uint32_t FP64Denormals =
  68     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
  69
  70   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
  71          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
  72          FP_DENORM_MODE_SP(FP32Denormals) |
  73          FP_DENORM_MODE_DP(FP64Denormals);
  74 }
  75
  76 static AsmPrinter *
  77 createAMDGPUAsmPrinterPass(TargetMachine &tm,
  78                            std::unique_ptr<MCStreamer> &&Streamer) {
  79   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
  80 }
  81
  82 extern "C" void LLVMInitializeR600AsmPrinter() {
  83   TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
  84   TargetRegistry::RegisterAsmPrinter(TheGCNTarget, createAMDGPUAsmPrinterPass);
  85 }
  86
  87 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
  88                                    std::unique_ptr<MCStreamer> Streamer)
  89     : AsmPrinter(TM, std::move(Streamer)) {
  90   DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode();
  91 }
  92
  93 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
  94
  95   // This label is used to mark the end of the .text section.
  96   const TargetLoweringObjectFile &TLOF = getObjFileLowering();
  97   OutStreamer.SwitchSection(TLOF.getTextSection());
  98   MCSymbol *EndOfTextLabel =
  99       OutContext.GetOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
 100   OutStreamer.EmitLabel(EndOfTextLabel);
 101 }
 102
 103 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 104
 105   // The starting address of all shader programs must be 256 bytes aligned.
 106   MF.setAlignment(8);
 107
 108   SetupMachineFunction(MF);
 109
 110   EmitFunctionHeader();
 111
 112   MCContext &Context = getObjFileLowering().getContext();
 113   const MCSectionELF *ConfigSection =
 114       Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
 115   OutStreamer.SwitchSection(ConfigSection);
 116
 117   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 118   SIProgramInfo KernelInfo;
 119   if (STM.isAmdHsaOS()) {
 120     getSIProgramInfo(KernelInfo, MF);
 121     EmitAmdKernelCodeT(MF, KernelInfo);
 122     OutStreamer.EmitCodeAlignment(2 << (MF.getAlignment() - 1));
 123   } else if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
 124     getSIProgramInfo(KernelInfo, MF);
 125     EmitProgramInfoSI(MF, KernelInfo);
 126   } else {
 127     EmitProgramInfoR600(MF);
 128   }
 129
 130   DisasmLines.clear();
 131   HexLines.clear();
 132   DisasmLineMaxLen = 0;
 133
 134   OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
 135   EmitFunctionBody();
 136
 137   if (isVerbose()) {
 138     const MCSectionELF *CommentSection =
 139         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
 140     OutStreamer.SwitchSection(CommentSection);
 141
 142     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
 143       OutStreamer.emitRawComment(" Kernel info:", false);
 144       OutStreamer.emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
 145                                  false);
 146       OutStreamer.emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
 147                                  false);
 148       OutStreamer.emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
 149                                  false);
 150       OutStreamer.emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
 151                                  false);
 152       OutStreamer.emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
 153                                  false);
 154       OutStreamer.emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
 155                                  false);
 156     } else {
 157       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 158       OutStreamer.emitRawComment(
 159         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
 160     }
 161   }
 162
 163   if (STM.dumpCode() && DisasmEnabled) {
 164
 165     OutStreamer.SwitchSection(
 166         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
 167
 168     for (size_t i = 0; i < DisasmLines.size(); ++i) {
 169       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
 170       Comment += " ; " + HexLines[i] + "\n";
 171
 172       OutStreamer.EmitBytes(StringRef(DisasmLines[i]));
 173       OutStreamer.EmitBytes(StringRef(Comment));
 174     }
 175   }
 176
 177   return false;
 178 }
 179
 180 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
 181   unsigned MaxGPR = 0;
 182   bool killPixel = false;
 183   const R600RegisterInfo *RI = static_cast<const R600RegisterInfo *>(
 184       TM.getSubtargetImpl()->getRegisterInfo());
 185   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 186   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 187
 188   for (const MachineBasicBlock &MBB : MF) {
 189     for (const MachineInstr &MI : MBB) {
 190       if (MI.getOpcode() == AMDGPU::KILLGT)
 191         killPixel = true;
 192       unsigned numOperands = MI.getNumOperands();
 193       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 194         const MachineOperand &MO = MI.getOperand(op_idx);
 195         if (!MO.isReg())
 196           continue;
 197         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
 198
 199         // Register with value > 127 aren't GPR
 200         if (HWReg > 127)
 201           continue;
 202         MaxGPR = std::max(MaxGPR, HWReg);
 203       }
 204     }
 205   }
 206
 207   unsigned RsrcReg;
 208   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
 209     // Evergreen / Northern Islands
 210     switch (MFI->getShaderType()) {
 211     default: // Fall through
 212     case ShaderType::COMPUTE:  RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
 213     case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
 214     case ShaderType::PIXEL:    RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
 215     case ShaderType::VERTEX:   RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
 216     }
 217   } else {
 218     // R600 / R700
 219     switch (MFI->getShaderType()) {
 220     default: // Fall through
 221     case ShaderType::GEOMETRY: // Fall through
 222     case ShaderType::COMPUTE:  // Fall through
 223     case ShaderType::VERTEX:   RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
 224     case ShaderType::PIXEL:    RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
 225     }
 226   }
 227
 228   OutStreamer.EmitIntValue(RsrcReg, 4);
 229   OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
 230                            S_STACK_SIZE(MFI->StackSize), 4);
 231   OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
 232   OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
 233
 234   if (MFI->getShaderType() == ShaderType::COMPUTE) {
 235     OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
 236     OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
 237   }
 238 }
 239
 240 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
 241                                         const MachineFunction &MF) const {
 242   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 243   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 244   uint64_t CodeSize = 0;
 245   unsigned MaxSGPR = 0;
 246   unsigned MaxVGPR = 0;
 247   bool VCCUsed = false;
 248   bool FlatUsed = false;
 249   const SIRegisterInfo *RI = static_cast<const SIRegisterInfo *>(
 250       TM.getSubtargetImpl()->getRegisterInfo());
 251
 252   for (const MachineBasicBlock &MBB : MF) {
 253     for (const MachineInstr &MI : MBB) {
 254       // TODO: CodeSize should account for multiple functions.
 255       CodeSize += MI.getDesc().Size;
 256
 257       unsigned numOperands = MI.getNumOperands();
 258       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 259         const MachineOperand &MO = MI.getOperand(op_idx);
 260         unsigned width = 0;
 261         bool isSGPR = false;
 262
 263         if (!MO.isReg()) {
 264           continue;
 265         }
 266         unsigned reg = MO.getReg();
 267         if (reg == AMDGPU::VCC || reg == AMDGPU::VCC_LO ||
 268             reg == AMDGPU::VCC_HI) {
 269           VCCUsed = true;
 270           continue;
 271         } else if (reg == AMDGPU::FLAT_SCR ||
 272                    reg == AMDGPU::FLAT_SCR_LO ||
 273                    reg == AMDGPU::FLAT_SCR_HI) {
 274           FlatUsed = true;
 275           continue;
 276         }
 277
 278         switch (reg) {
 279         default: break;
 280         case AMDGPU::SCC:
 281         case AMDGPU::EXEC:
 282         case AMDGPU::M0:
 283           continue;
 284         }
 285
 286         if (AMDGPU::SReg_32RegClass.contains(reg)) {
 287           isSGPR = true;
 288           width = 1;
 289         } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
 290           isSGPR = false;
 291           width = 1;
 292         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
 293           isSGPR = true;
 294           width = 2;
 295         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
 296           isSGPR = false;
 297           width = 2;
 298         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
 299           isSGPR = false;
 300           width = 3;
 301         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
 302           isSGPR = true;
 303           width = 4;
 304         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
 305           isSGPR = false;
 306           width = 4;
 307         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
 308           isSGPR = true;
 309           width = 8;
 310         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
 311           isSGPR = false;
 312           width = 8;
 313         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
 314           isSGPR = true;
 315           width = 16;
 316         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
 317           isSGPR = false;
 318           width = 16;
 319         } else {
 320           llvm_unreachable("Unknown register class");
 321         }
 322         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
 323         unsigned maxUsed = hwReg + width - 1;
 324         if (isSGPR) {
 325           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
 326         } else {
 327           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
 328         }
 329       }
 330     }
 331   }
 332
 333   if (VCCUsed)
 334     MaxSGPR += 2;
 335
 336   if (FlatUsed)
 337     MaxSGPR += 2;
 338
 339   // We found the maximum register index. They start at 0, so add one to get the
 340   // number of registers.
 341   ProgInfo.NumVGPR = MaxVGPR + 1;
 342   ProgInfo.NumSGPR = MaxSGPR + 1;
 343
 344   ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
 345   ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
 346   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
 347   // register.
 348   ProgInfo.FloatMode = getFPMode(MF);
 349
 350   // XXX: Not quite sure what this does, but sc seems to unset this.
 351   ProgInfo.IEEEMode = 0;
 352
 353   // Do not clamp NAN to 0.
 354   ProgInfo.DX10Clamp = 0;
 355
 356   const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
 357   ProgInfo.ScratchSize = FrameInfo->estimateStackSize(MF);
 358
 359   ProgInfo.FlatUsed = FlatUsed;
 360   ProgInfo.VCCUsed = VCCUsed;
 361   ProgInfo.CodeLen = CodeSize;
 362
 363   unsigned LDSAlignShift;
 364   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
 365     // LDS is allocated in 64 dword blocks.
 366     LDSAlignShift = 8;
 367   } else {
 368     // LDS is allocated in 128 dword blocks.
 369     LDSAlignShift = 9;
 370   }
 371
 372   unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
 373                           MFI->getMaximumWorkGroupSize(MF);
 374
 375   ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;
 376   ProgInfo.LDSBlocks =
 377      RoundUpToAlignment(ProgInfo.LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
 378
 379   // Scratch is allocated in 256 dword blocks.
 380   unsigned ScratchAlignShift = 10;
 381   // We need to program the hardware with the amount of scratch memory that
 382   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
 383   // scratch memory used per thread.
 384   ProgInfo.ScratchBlocks =
 385     RoundUpToAlignment(ProgInfo.ScratchSize * STM.getWavefrontSize(),
 386                        1 << ScratchAlignShift) >> ScratchAlignShift;
 387
 388   ProgInfo.ComputePGMRSrc1 =
 389       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
 390       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
 391       S_00B848_PRIORITY(ProgInfo.Priority) |
 392       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
 393       S_00B848_PRIV(ProgInfo.Priv) |
 394       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
 395       S_00B848_IEEE_MODE(ProgInfo.DebugMode) |
 396       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
 397
 398   ProgInfo.ComputePGMRSrc2 =
 399       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
 400       S_00B84C_USER_SGPR(MFI->NumUserSGPRs) |
 401       S_00B84C_TGID_X_EN(1) |
 402       S_00B84C_TGID_Y_EN(1) |
 403       S_00B84C_TGID_Z_EN(1) |
 404       S_00B84C_TG_SIZE_EN(1) |
 405       S_00B84C_TIDIG_COMP_CNT(2) |
 406       S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks);
 407 }
 408
 409 static unsigned getRsrcReg(unsigned ShaderType) {
 410   switch (ShaderType) {
 411   default: // Fall through
 412   case ShaderType::COMPUTE:  return R_00B848_COMPUTE_PGM_RSRC1;
 413   case ShaderType::GEOMETRY: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
 414   case ShaderType::PIXEL:    return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
 415   case ShaderType::VERTEX:   return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
 416   }
 417 }
 418
 419 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
 420                                          const SIProgramInfo &KernelInfo) {
 421   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 422   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 423   unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
 424
 425   if (MFI->getShaderType() == ShaderType::COMPUTE) {
 426     OutStreamer.EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
 427
 428     OutStreamer.EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
 429
 430     OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
 431     OutStreamer.EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
 432
 433     OutStreamer.EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
 434     OutStreamer.EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
 435
 436     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
 437     // 0" comment but I don't see a corresponding field in the register spec.
 438   } else {
 439     OutStreamer.EmitIntValue(RsrcReg, 4);
 440     OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
 441                              S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
 442     if (STM.isVGPRSpillingEnabled(MFI)) {
 443       OutStreamer.EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
 444       OutStreamer.EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
 445     }
 446   }
 447
 448   if (MFI->getShaderType() == ShaderType::PIXEL) {
 449     OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
 450     OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
 451     OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
 452     OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);
 453   }
 454 }
 455
 456 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
 457                                         const SIProgramInfo &KernelInfo) const {
 458   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 459   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 460   amd_kernel_code_t header;
 461
 462   memset(&header, 0, sizeof(header));
 463
 464   header.amd_code_version_major = AMD_CODE_VERSION_MAJOR;
 465   header.amd_code_version_minor = AMD_CODE_VERSION_MINOR;
 466
 467   header.struct_byte_size = sizeof(amd_kernel_code_t);
 468
 469   header.target_chip = STM.getAmdKernelCodeChipID();
 470
 471   header.kernel_code_entry_byte_offset = (1ULL << MF.getAlignment());
 472
 473   header.compute_pgm_resource_registers =
 474       KernelInfo.ComputePGMRSrc1 |
 475       (KernelInfo.ComputePGMRSrc2 << 32);
 476
 477   // Code Properties:
 478   header.code_properties = AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR |
 479                            AMD_CODE_PROPERTY_IS_PTR64;
 480
 481   if (KernelInfo.FlatUsed)
 482     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
 483
 484   if (KernelInfo.ScratchBlocks)
 485     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE;
 486
 487   header.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
 488   header.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
 489
 490   // MFI->ABIArgOffset is the number of bytes for the kernel arguments
 491   // plus 36.  36 is the number of bytes reserved at the begining of the
 492   // input buffer to store work-group size information.
 493   // FIXME: We should be adding the size of the implicit arguments
 494   // to this value.
 495   header.kernarg_segment_byte_size = MFI->ABIArgOffset;
 496
 497   header.wavefront_sgpr_count = KernelInfo.NumSGPR;
 498   header.workitem_vgpr_count = KernelInfo.NumVGPR;
 499
 500   // FIXME: What values do I put for these alignments
 501   header.kernarg_segment_alignment = 0;
 502   header.group_segment_alignment = 0;
 503   header.private_segment_alignment = 0;
 504
 505   header.code_type = 1; // HSA_EXT_CODE_KERNEL
 506
 507   header.wavefront_size = STM.getWavefrontSize();
 508
 509   const MCSectionELF *VersionSection =
 510       OutContext.getELFSection(".hsa.version", ELF::SHT_PROGBITS, 0);
 511   OutStreamer.SwitchSection(VersionSection);
 512   OutStreamer.EmitBytes(Twine("HSA Code Unit:" +
 513                         Twine(header.hsail_version_major) + "." +
 514                         Twine(header.hsail_version_minor) + ":" +
 515                         "AMD:" +
 516                         Twine(header.amd_code_version_major) + "." +
 517                         Twine(header.amd_code_version_minor) +  ":" +
 518                         "GFX8.1:0").str());
 519
 520   OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
 521
 522   if (isVerbose()) {
 523     OutStreamer.emitRawComment("amd_code_version_major = " +
 524                                Twine(header.amd_code_version_major), false);
 525     OutStreamer.emitRawComment("amd_code_version_minor = " +
 526                                Twine(header.amd_code_version_minor), false);
 527     OutStreamer.emitRawComment("struct_byte_size = " +
 528                                Twine(header.struct_byte_size), false);
 529     OutStreamer.emitRawComment("target_chip = " +
 530                                Twine(header.target_chip), false);
 531     OutStreamer.emitRawComment(" compute_pgm_rsrc1: " +
 532                                Twine::utohexstr(KernelInfo.ComputePGMRSrc1), false);
 533     OutStreamer.emitRawComment(" compute_pgm_rsrc2: " +
 534                                Twine::utohexstr(KernelInfo.ComputePGMRSrc2), false);
 535     OutStreamer.emitRawComment("enable_sgpr_private_segment_buffer = " +
 536       Twine((bool)(header.code_properties &
 537                    AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE)), false);
 538     OutStreamer.emitRawComment("enable_sgpr_kernarg_segment_ptr = " +
 539       Twine((bool)(header.code_properties &
 540                    AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)), false);
 541     OutStreamer.emitRawComment("private_element_size = 2 ", false);
 542     OutStreamer.emitRawComment("is_ptr64 = " +
 543         Twine((bool)(header.code_properties & AMD_CODE_PROPERTY_IS_PTR64)), false);
 544     OutStreamer.emitRawComment("workitem_private_segment_byte_size = " +
 545                                Twine(header.workitem_private_segment_byte_size),
 546                                false);
 547     OutStreamer.emitRawComment("workgroup_group_segment_byte_size = " +
 548                                Twine(header.workgroup_group_segment_byte_size),
 549                                false);
 550     OutStreamer.emitRawComment("gds_segment_byte_size = " +
 551                                Twine(header.gds_segment_byte_size), false);
 552     OutStreamer.emitRawComment("kernarg_segment_byte_size = " +
 553                                Twine(header.kernarg_segment_byte_size), false);
 554     OutStreamer.emitRawComment("wavefront_sgpr_count = " +
 555                                Twine(header.wavefront_sgpr_count), false);
 556     OutStreamer.emitRawComment("workitem_vgpr_count = " +
 557                                Twine(header.workitem_vgpr_count), false);
 558     OutStreamer.emitRawComment("code_type = " + Twine(header.code_type), false);
 559     OutStreamer.emitRawComment("wavefront_size = " +
 560                                Twine((int)header.wavefront_size), false);
 561     OutStreamer.emitRawComment("optimization_level = " +
 562                                Twine(header.optimization_level), false);
 563     OutStreamer.emitRawComment("hsail_profile = " +
 564                                Twine(header.hsail_profile), false);
 565     OutStreamer.emitRawComment("hsail_machine_model = " +
 566                                Twine(header.hsail_machine_model), false);
 567     OutStreamer.emitRawComment("hsail_version_major = " +
 568                                Twine(header.hsail_version_major), false);
 569     OutStreamer.emitRawComment("hsail_version_minor = " +
 570                                Twine(header.hsail_version_minor), false);
 571   }
 572
 573   OutStreamer.EmitBytes(StringRef((char*)&header, sizeof(header)));
 574 }