lib/Target/R600/AMDGPUAsmPrinter.cpp

   1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 ///
  12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
  13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
  14 /// an MCObjectStreamer it outputs binary code.
  15 //
  16 //===----------------------------------------------------------------------===//
  17 //
  18
  19 #include "AMDGPUAsmPrinter.h"
  20 #include "AMDGPU.h"
  21 #include "AMDGPUSubtarget.h"
  22 #include "R600Defines.h"
  23 #include "R600MachineFunctionInfo.h"
  24 #include "R600RegisterInfo.h"
  25 #include "SIDefines.h"
  26 #include "SIMachineFunctionInfo.h"
  27 #include "SIRegisterInfo.h"
  28 #include "llvm/MC/MCContext.h"
  29 #include "llvm/MC/MCSectionELF.h"
  30 #include "llvm/MC/MCStreamer.h"
  31 #include "llvm/Support/ELF.h"
  32 #include "llvm/Support/MathExtras.h"
  33 #include "llvm/Support/TargetRegistry.h"
  34 #include "llvm/Target/TargetLoweringObjectFile.h"
  35
  36 using namespace llvm;
  37
  38 // TODO: This should get the default rounding mode from the kernel. We just set
  39 // the default here, but this could change if the OpenCL rounding mode pragmas
  40 // are used.
  41 //
  42 // The denormal mode here should match what is reported by the OpenCL runtime
  43 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
  44 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
  45 //
  46 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
  47 // precision, and leaves single precision to flush all and does not report
  48 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
  49 // CL_FP_DENORM for both.
  50 static uint32_t getFPMode(MachineFunction &) {
  51   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
  52          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
  53          FP_DENORM_MODE_SP(FP_DENORM_FLUSH_NONE) |
  54          FP_DENORM_MODE_DP(FP_DENORM_FLUSH_NONE);
  55 }
  56
  57 static AsmPrinter *createAMDGPUAsmPrinterPass(TargetMachine &tm,
  58                                               MCStreamer &Streamer) {
  59   return new AMDGPUAsmPrinter(tm, Streamer);
  60 }
  61
  62 extern "C" void LLVMInitializeR600AsmPrinter() {
  63   TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
  64 }
  65
  66 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
  67     : AsmPrinter(TM, Streamer) {
  68   DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode();
  69 }
  70
  71 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
  72   SetupMachineFunction(MF);
  73
  74   OutStreamer.emitRawComment(Twine('@') + MF.getName() + Twine(':'));
  75
  76   MCContext &Context = getObjFileLowering().getContext();
  77   const MCSectionELF *ConfigSection = Context.getELFSection(".AMDGPU.config",
  78                                               ELF::SHT_PROGBITS, 0,
  79                                               SectionKind::getReadOnly());
  80   OutStreamer.SwitchSection(ConfigSection);
  81
  82   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
  83   SIProgramInfo KernelInfo;
  84   if (STM.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
  85     getSIProgramInfo(KernelInfo, MF);
  86     EmitProgramInfoSI(MF, KernelInfo);
  87   } else {
  88     EmitProgramInfoR600(MF);
  89   }
  90
  91   DisasmLines.clear();
  92   HexLines.clear();
  93   DisasmLineMaxLen = 0;
  94
  95   OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
  96   EmitFunctionBody();
  97
  98   if (isVerbose()) {
  99     const MCSectionELF *CommentSection
 100       = Context.getELFSection(".AMDGPU.csdata",
 101                               ELF::SHT_PROGBITS, 0,
 102                               SectionKind::getReadOnly());
 103     OutStreamer.SwitchSection(CommentSection);
 104
 105     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
 106       OutStreamer.emitRawComment(" Kernel info:", false);
 107       OutStreamer.emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
 108                                  false);
 109       OutStreamer.emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
 110                                  false);
 111       OutStreamer.emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
 112                                  false);
 113       OutStreamer.emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
 114                                  false);
 115       OutStreamer.emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
 116                                  false);
 117     } else {
 118       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 119       OutStreamer.emitRawComment(
 120         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
 121     }
 122   }
 123
 124   if (STM.dumpCode()) {
 125 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 126     MF.dump();
 127 #endif
 128
 129     if (DisasmEnabled) {
 130       OutStreamer.SwitchSection(Context.getELFSection(".AMDGPU.disasm",
 131                                                   ELF::SHT_NOTE, 0,
 132                                                   SectionKind::getReadOnly()));
 133
 134       for (size_t i = 0; i < DisasmLines.size(); ++i) {
 135         std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
 136         Comment += " ; " + HexLines[i] + "\n";
 137
 138         OutStreamer.EmitBytes(StringRef(DisasmLines[i]));
 139         OutStreamer.EmitBytes(StringRef(Comment));
 140       }
 141     }
 142   }
 143
 144   return false;
 145 }
 146
 147 void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) {
 148   unsigned MaxGPR = 0;
 149   bool killPixel = false;
 150   const R600RegisterInfo * RI =
 151                 static_cast<const R600RegisterInfo*>(TM.getRegisterInfo());
 152   R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 153   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 154
 155   for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
 156                                                   BB != BB_E; ++BB) {
 157     MachineBasicBlock &MBB = *BB;
 158     for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
 159                                                     I != E; ++I) {
 160       MachineInstr &MI = *I;
 161       if (MI.getOpcode() == AMDGPU::KILLGT)
 162         killPixel = true;
 163       unsigned numOperands = MI.getNumOperands();
 164       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 165         MachineOperand & MO = MI.getOperand(op_idx);
 166         if (!MO.isReg())
 167           continue;
 168         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
 169
 170         // Register with value > 127 aren't GPR
 171         if (HWReg > 127)
 172           continue;
 173         MaxGPR = std::max(MaxGPR, HWReg);
 174       }
 175     }
 176   }
 177
 178   unsigned RsrcReg;
 179   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
 180     // Evergreen / Northern Islands
 181     switch (MFI->getShaderType()) {
 182     default: // Fall through
 183     case ShaderType::COMPUTE:  RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
 184     case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
 185     case ShaderType::PIXEL:    RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
 186     case ShaderType::VERTEX:   RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
 187     }
 188   } else {
 189     // R600 / R700
 190     switch (MFI->getShaderType()) {
 191     default: // Fall through
 192     case ShaderType::GEOMETRY: // Fall through
 193     case ShaderType::COMPUTE:  // Fall through
 194     case ShaderType::VERTEX:   RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
 195     case ShaderType::PIXEL:    RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
 196     }
 197   }
 198
 199   OutStreamer.EmitIntValue(RsrcReg, 4);
 200   OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
 201                            S_STACK_SIZE(MFI->StackSize), 4);
 202   OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
 203   OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
 204
 205   if (MFI->getShaderType() == ShaderType::COMPUTE) {
 206     OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
 207     OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
 208   }
 209 }
 210
 211 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
 212                                         MachineFunction &MF) const {
 213   uint64_t CodeSize = 0;
 214   unsigned MaxSGPR = 0;
 215   unsigned MaxVGPR = 0;
 216   bool VCCUsed = false;
 217   const SIRegisterInfo * RI =
 218                 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
 219
 220   for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
 221                                                   BB != BB_E; ++BB) {
 222     MachineBasicBlock &MBB = *BB;
 223     for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
 224                                                     I != E; ++I) {
 225       MachineInstr &MI = *I;
 226
 227       // TODO: CodeSize should account for multiple functions.
 228       CodeSize += MI.getDesc().Size;
 229
 230       unsigned numOperands = MI.getNumOperands();
 231       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 232         MachineOperand &MO = MI.getOperand(op_idx);
 233         unsigned width = 0;
 234         bool isSGPR = false;
 235
 236         if (!MO.isReg()) {
 237           continue;
 238         }
 239         unsigned reg = MO.getReg();
 240         if (reg == AMDGPU::VCC || reg == AMDGPU::VCC_LO ||
 241             reg == AMDGPU::VCC_HI) {
 242           VCCUsed = true;
 243           continue;
 244         }
 245
 246         switch (reg) {
 247         default: break;
 248         case AMDGPU::SCC:
 249         case AMDGPU::EXEC:
 250         case AMDGPU::M0:
 251           continue;
 252         }
 253
 254         if (AMDGPU::SReg_32RegClass.contains(reg)) {
 255           isSGPR = true;
 256           width = 1;
 257         } else if (AMDGPU::VReg_32RegClass.contains(reg)) {
 258           isSGPR = false;
 259           width = 1;
 260         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
 261           isSGPR = true;
 262           width = 2;
 263         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
 264           isSGPR = false;
 265           width = 2;
 266         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
 267           isSGPR = false;
 268           width = 3;
 269         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
 270           isSGPR = true;
 271           width = 4;
 272         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
 273           isSGPR = false;
 274           width = 4;
 275         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
 276           isSGPR = true;
 277           width = 8;
 278         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
 279           isSGPR = false;
 280           width = 8;
 281         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
 282           isSGPR = true;
 283           width = 16;
 284         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
 285           isSGPR = false;
 286           width = 16;
 287         } else {
 288           llvm_unreachable("Unknown register class");
 289         }
 290         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
 291         unsigned maxUsed = hwReg + width - 1;
 292         if (isSGPR) {
 293           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
 294         } else {
 295           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
 296         }
 297       }
 298     }
 299   }
 300
 301   if (VCCUsed)
 302     MaxSGPR += 2;
 303
 304   ProgInfo.NumVGPR = MaxVGPR;
 305   ProgInfo.NumSGPR = MaxSGPR;
 306
 307   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
 308   // register.
 309   ProgInfo.FloatMode = getFPMode(MF);
 310
 311   // XXX: Not quite sure what this does, but sc seems to unset this.
 312   ProgInfo.IEEEMode = 0;
 313
 314   // Do not clamp NAN to 0.
 315   ProgInfo.DX10Clamp = 0;
 316
 317   ProgInfo.CodeLen = CodeSize;
 318 }
 319
 320 void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF,
 321                                          const SIProgramInfo &KernelInfo) {
 322   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 323   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 324
 325   unsigned RsrcReg;
 326   switch (MFI->getShaderType()) {
 327   default: // Fall through
 328   case ShaderType::COMPUTE:  RsrcReg = R_00B848_COMPUTE_PGM_RSRC1; break;
 329   case ShaderType::GEOMETRY: RsrcReg = R_00B228_SPI_SHADER_PGM_RSRC1_GS; break;
 330   case ShaderType::PIXEL:    RsrcReg = R_00B028_SPI_SHADER_PGM_RSRC1_PS; break;
 331   case ShaderType::VERTEX:   RsrcReg = R_00B128_SPI_SHADER_PGM_RSRC1_VS; break;
 332   }
 333
 334   unsigned LDSAlignShift;
 335   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
 336     // LDS is allocated in 64 dword blocks.
 337     LDSAlignShift = 8;
 338   } else {
 339     // LDS is allocated in 128 dword blocks.
 340     LDSAlignShift = 9;
 341   }
 342
 343   unsigned LDSBlocks =
 344     RoundUpToAlignment(MFI->LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
 345
 346   if (MFI->getShaderType() == ShaderType::COMPUTE) {
 347     OutStreamer.EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
 348
 349     const uint32_t ComputePGMRSrc1 =
 350       S_00B848_VGPRS(KernelInfo.NumVGPR / 4) |
 351       S_00B848_SGPRS(KernelInfo.NumSGPR / 8) |
 352       S_00B848_PRIORITY(KernelInfo.Priority) |
 353       S_00B848_FLOAT_MODE(KernelInfo.FloatMode) |
 354       S_00B848_PRIV(KernelInfo.Priv) |
 355       S_00B848_DX10_CLAMP(KernelInfo.DX10Clamp) |
 356       S_00B848_IEEE_MODE(KernelInfo.DebugMode) |
 357       S_00B848_IEEE_MODE(KernelInfo.IEEEMode);
 358
 359     OutStreamer.EmitIntValue(ComputePGMRSrc1, 4);
 360
 361     OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
 362     OutStreamer.EmitIntValue(S_00B84C_LDS_SIZE(LDSBlocks), 4);
 363   } else {
 364     OutStreamer.EmitIntValue(RsrcReg, 4);
 365     OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.NumVGPR / 4) |
 366                              S_00B028_SGPRS(KernelInfo.NumSGPR / 8), 4);
 367   }
 368
 369   if (MFI->getShaderType() == ShaderType::PIXEL) {
 370     OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
 371     OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(LDSBlocks), 4);
 372     OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
 373     OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);
 374   }
 375 }