1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
16 #include "PPCTargetObjectFile.h"
17 #include "PPCTargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Transforms/Scalar.h"
30 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
31 cl::desc("Disable CTR loops for PPC"));
34 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
35 cl::desc("Disable PPC loop preinc prep"));
38 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
39 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
42 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
43 cl::desc("Enable optimizations on complex GEPs"),
46 extern "C" void LLVMInitializePowerPCTarget() {
47 // Register the targets
48 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
49 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
50 RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
53 /// Return the datalayout string of a subtarget.
54 static std::string getDataLayoutString(const Triple &T) {
55 bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
58 // Most PPC* platforms are big endian, PPC64LE is little endian.
59 if (T.getArch() == Triple::ppc64le)
64 Ret += DataLayout::getManglingComponent(T);
66 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
68 if (!is64Bit || T.getOS() == Triple::Lv2)
71 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
72 // documentation are wrong; these are correct (i.e. "what gcc does").
73 if (is64Bit || !T.isOSDarwin())
78 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
87 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
88 std::string FullFS = FS;
89 Triple TargetTriple(TT);
91 // Make sure 64-bit features are available when CPUname is generic
92 if (TargetTriple.getArch() == Triple::ppc64 ||
93 TargetTriple.getArch() == Triple::ppc64le) {
95 FullFS = "+64bit," + FullFS;
100 if (OL >= CodeGenOpt::Default) {
102 FullFS = "+crbits," + FullFS;
107 if (OL != CodeGenOpt::None) {
109 FullFS = "+invariant-function-descriptors," + FullFS;
111 FullFS = "+invariant-function-descriptors";
117 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
118 // If it isn't a Mach-O file then it's going to be a linux ELF
121 return make_unique<TargetLoweringObjectFileMachO>();
123 return make_unique<PPC64LinuxTargetObjectFile>();
126 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
127 const TargetOptions &Options) {
128 if (Options.MCOptions.getABIName().startswith("elfv1"))
129 return PPCTargetMachine::PPC_ABI_ELFv1;
130 else if (Options.MCOptions.getABIName().startswith("elfv2"))
131 return PPCTargetMachine::PPC_ABI_ELFv2;
133 assert(Options.MCOptions.getABIName().empty() &&
134 "Unknown target-abi option!");
136 if (!TT.isMacOSX()) {
137 switch (TT.getArch()) {
138 case Triple::ppc64le:
139 return PPCTargetMachine::PPC_ABI_ELFv2;
141 return PPCTargetMachine::PPC_ABI_ELFv1;
147 return PPCTargetMachine::PPC_ABI_UNKNOWN;
150 // The FeatureString here is a little subtle. We are modifying the feature string
151 // with what are (currently) non-function specific overrides as it goes into the
152 // LLVMTargetMachine constructor and then using the stored value in the
153 // Subtarget constructor below it.
154 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
155 StringRef FS, const TargetOptions &Options,
156 Reloc::Model RM, CodeModel::Model CM,
157 CodeGenOpt::Level OL)
158 : LLVMTargetMachine(T, TT, CPU, computeFSAdditions(FS, OL, TT), Options, RM,
160 TLOF(createTLOF(Triple(getTargetTriple()))),
161 TargetABI(computeTargetABI(Triple(TT), Options)),
162 DL(getDataLayoutString(Triple(TT))), Subtarget(TT, CPU, TargetFS, *this) {
166 PPCTargetMachine::~PPCTargetMachine() {}
168 void PPC32TargetMachine::anchor() { }
170 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
171 StringRef CPU, StringRef FS,
172 const TargetOptions &Options,
173 Reloc::Model RM, CodeModel::Model CM,
174 CodeGenOpt::Level OL)
175 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
178 void PPC64TargetMachine::anchor() { }
180 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
181 StringRef CPU, StringRef FS,
182 const TargetOptions &Options,
183 Reloc::Model RM, CodeModel::Model CM,
184 CodeGenOpt::Level OL)
185 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
189 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
190 Attribute CPUAttr = F.getFnAttribute("target-cpu");
191 Attribute FSAttr = F.getFnAttribute("target-features");
193 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
194 ? CPUAttr.getValueAsString().str()
196 std::string FS = !FSAttr.hasAttribute(Attribute::None)
197 ? FSAttr.getValueAsString().str()
200 auto &I = SubtargetMap[CPU + FS];
202 // This needs to be done before we create a new subtarget since any
203 // creation will depend on the TM and the code generation flags on the
204 // function that reside in TargetOptions.
205 resetTargetOptions(F);
206 I = llvm::make_unique<PPCSubtarget>(TargetTriple, CPU, FS, *this);
211 //===----------------------------------------------------------------------===//
212 // Pass Pipeline Configuration
213 //===----------------------------------------------------------------------===//
216 /// PPC Code Generator Pass Configuration Options.
217 class PPCPassConfig : public TargetPassConfig {
219 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
220 : TargetPassConfig(TM, PM) {}
222 PPCTargetMachine &getPPCTargetMachine() const {
223 return getTM<PPCTargetMachine>();
226 void addIRPasses() override;
227 bool addPreISel() override;
228 bool addILPOpts() override;
229 bool addInstSelector() override;
230 void addPreRegAlloc() override;
231 void addPreSched2() override;
232 void addPreEmitPass() override;
236 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
237 return new PPCPassConfig(this, PM);
240 void PPCPassConfig::addIRPasses() {
241 addPass(createAtomicExpandPass(&getPPCTargetMachine()));
243 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
244 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
245 // and lower a GEP with multiple indices to either arithmetic operations or
246 // multiple GEPs with single index.
247 addPass(createSeparateConstOffsetFromGEPPass(TM, true));
248 // Call EarlyCSE pass to find and remove subexpressions in the lowered
250 addPass(createEarlyCSEPass());
251 // Do loop invariant code motion in case part of the lowered result is
253 addPass(createLICMPass());
256 TargetPassConfig::addIRPasses();
259 bool PPCPassConfig::addPreISel() {
260 if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
261 addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
263 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
264 addPass(createPPCCTRLoops(getPPCTargetMachine()));
269 bool PPCPassConfig::addILPOpts() {
270 addPass(&EarlyIfConverterID);
274 bool PPCPassConfig::addInstSelector() {
275 // Install an instruction selector.
276 addPass(createPPCISelDag(getPPCTargetMachine()));
279 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
280 addPass(createPPCCTRLoopsVerify());
283 addPass(createPPCVSXCopyPass());
287 void PPCPassConfig::addPreRegAlloc() {
288 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
289 insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
291 if (getPPCTargetMachine().getRelocationModel() == Reloc::PIC_)
292 addPass(createPPCTLSDynamicCallPass());
295 void PPCPassConfig::addPreSched2() {
296 if (getOptLevel() != CodeGenOpt::None)
297 addPass(&IfConverterID);
300 void PPCPassConfig::addPreEmitPass() {
301 if (getOptLevel() != CodeGenOpt::None)
302 addPass(createPPCEarlyReturnPass(), false);
303 // Must run branch selection immediately preceding the asm printer.
304 addPass(createPPCBranchSelectionPass(), false);
307 TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
308 return TargetIRAnalysis(
309 [this](Function &F) { return TargetTransformInfo(PPCTTIImpl(this, F)); });