1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
26 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27 cl::desc("Disable CTR loops for PPC"));
30 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
31 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
33 extern "C" void LLVMInitializePowerPCTarget() {
34 // Register the targets
35 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
36 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
37 RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
40 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
41 StringRef FS, const TargetOptions &Options,
42 Reloc::Model RM, CodeModel::Model CM,
43 CodeGenOpt::Level OL, bool is64Bit)
44 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
45 Subtarget(TT, CPU, FS, is64Bit, OL), JITInfo(Subtarget),
46 TLInfo(*this), TSInfo(*this) {
50 void PPC32TargetMachine::anchor() { }
52 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
53 StringRef CPU, StringRef FS,
54 const TargetOptions &Options,
55 Reloc::Model RM, CodeModel::Model CM,
57 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
60 void PPC64TargetMachine::anchor() { }
62 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
63 StringRef CPU, StringRef FS,
64 const TargetOptions &Options,
65 Reloc::Model RM, CodeModel::Model CM,
67 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
71 //===----------------------------------------------------------------------===//
72 // Pass Pipeline Configuration
73 //===----------------------------------------------------------------------===//
76 /// PPC Code Generator Pass Configuration Options.
77 class PPCPassConfig : public TargetPassConfig {
79 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
80 : TargetPassConfig(TM, PM) {}
82 PPCTargetMachine &getPPCTargetMachine() const {
83 return getTM<PPCTargetMachine>();
86 const PPCSubtarget &getPPCSubtarget() const {
87 return *getPPCTargetMachine().getSubtargetImpl();
90 bool addPreISel() override;
91 bool addILPOpts() override;
92 bool addInstSelector() override;
93 bool addPreRegAlloc() override;
94 bool addPreSched2() override;
95 bool addPreEmitPass() override;
99 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
100 return new PPCPassConfig(this, PM);
103 bool PPCPassConfig::addPreISel() {
104 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
105 addPass(createPPCCTRLoops(getPPCTargetMachine()));
110 bool PPCPassConfig::addILPOpts() {
111 addPass(&EarlyIfConverterID);
115 bool PPCPassConfig::addInstSelector() {
116 // Install an instruction selector.
117 addPass(createPPCISelDag(getPPCTargetMachine()));
120 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
121 addPass(createPPCCTRLoopsVerify());
124 addPass(createPPCVSXCopyPass());
128 bool PPCPassConfig::addPreRegAlloc() {
129 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
130 insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
135 bool PPCPassConfig::addPreSched2() {
136 addPass(createPPCVSXCopyCleanupPass());
138 if (getOptLevel() != CodeGenOpt::None)
139 addPass(&IfConverterID);
144 bool PPCPassConfig::addPreEmitPass() {
145 if (getOptLevel() != CodeGenOpt::None)
146 addPass(createPPCEarlyReturnPass());
147 // Must run branch selection immediately preceding the asm printer.
148 addPass(createPPCBranchSelectionPass());
152 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
153 JITCodeEmitter &JCE) {
154 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
156 Subtarget.SetJITMode();
158 // Machine code emitter pass for PowerPC.
159 PM.add(createPPCJITCodeEmitterPass(*this, JCE));
164 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
165 // Add first the target-independent BasicTTI pass, then our PPC pass. This
166 // allows the PPC pass to delegate to the target independent layer when
168 PM.add(createBasicTargetTransformInfoPass(this));
169 PM.add(createPPCTargetTransformInfoPass(this));