1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
16 #include "PPCTargetObjectFile.h"
17 #include "PPCTargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Transforms/Scalar.h"
30 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
31 cl::desc("Disable CTR loops for PPC"));
34 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
35 cl::desc("Disable PPC loop preinc prep"));
38 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
39 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
42 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
43 cl::desc("Disable VSX Swap Removal for PPC"));
46 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
47 cl::desc("Enable optimizations on complex GEPs"),
51 EnablePrefetch("enable-ppc-prefetching",
52 cl::desc("disable software prefetching on PPC"),
53 cl::init(false), cl::Hidden);
55 extern "C" void LLVMInitializePowerPCTarget() {
56 // Register the targets
57 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
58 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
59 RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
62 /// Return the datalayout string of a subtarget.
63 static std::string getDataLayoutString(const Triple &T) {
64 bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
67 // Most PPC* platforms are big endian, PPC64LE is little endian.
68 if (T.getArch() == Triple::ppc64le)
73 Ret += DataLayout::getManglingComponent(T);
75 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
77 if (!is64Bit || T.getOS() == Triple::Lv2)
80 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
81 // documentation are wrong; these are correct (i.e. "what gcc does").
82 if (is64Bit || !T.isOSDarwin())
87 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
96 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
97 std::string FullFS = FS;
98 Triple TargetTriple(TT);
100 // Make sure 64-bit features are available when CPUname is generic
101 if (TargetTriple.getArch() == Triple::ppc64 ||
102 TargetTriple.getArch() == Triple::ppc64le) {
104 FullFS = "+64bit," + FullFS;
109 if (OL >= CodeGenOpt::Default) {
111 FullFS = "+crbits," + FullFS;
116 if (OL != CodeGenOpt::None) {
118 FullFS = "+invariant-function-descriptors," + FullFS;
120 FullFS = "+invariant-function-descriptors";
126 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
127 // If it isn't a Mach-O file then it's going to be a linux ELF
130 return make_unique<TargetLoweringObjectFileMachO>();
132 return make_unique<PPC64LinuxTargetObjectFile>();
135 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
136 const TargetOptions &Options) {
137 if (Options.MCOptions.getABIName().startswith("elfv1"))
138 return PPCTargetMachine::PPC_ABI_ELFv1;
139 else if (Options.MCOptions.getABIName().startswith("elfv2"))
140 return PPCTargetMachine::PPC_ABI_ELFv2;
142 assert(Options.MCOptions.getABIName().empty() &&
143 "Unknown target-abi option!");
145 if (!TT.isMacOSX()) {
146 switch (TT.getArch()) {
147 case Triple::ppc64le:
148 return PPCTargetMachine::PPC_ABI_ELFv2;
150 return PPCTargetMachine::PPC_ABI_ELFv1;
156 return PPCTargetMachine::PPC_ABI_UNKNOWN;
159 // The FeatureString here is a little subtle. We are modifying the feature string
160 // with what are (currently) non-function specific overrides as it goes into the
161 // LLVMTargetMachine constructor and then using the stored value in the
162 // Subtarget constructor below it.
163 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
164 StringRef FS, const TargetOptions &Options,
165 Reloc::Model RM, CodeModel::Model CM,
166 CodeGenOpt::Level OL)
167 : LLVMTargetMachine(T, getDataLayoutString(Triple(TT)), TT, CPU,
168 computeFSAdditions(FS, OL, TT), Options, RM, CM, OL),
169 TLOF(createTLOF(Triple(getTargetTriple()))),
170 TargetABI(computeTargetABI(Triple(TT), Options)) {
174 PPCTargetMachine::~PPCTargetMachine() {}
176 void PPC32TargetMachine::anchor() { }
178 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
179 StringRef CPU, StringRef FS,
180 const TargetOptions &Options,
181 Reloc::Model RM, CodeModel::Model CM,
182 CodeGenOpt::Level OL)
183 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
186 void PPC64TargetMachine::anchor() { }
188 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
189 StringRef CPU, StringRef FS,
190 const TargetOptions &Options,
191 Reloc::Model RM, CodeModel::Model CM,
192 CodeGenOpt::Level OL)
193 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
197 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
198 Attribute CPUAttr = F.getFnAttribute("target-cpu");
199 Attribute FSAttr = F.getFnAttribute("target-features");
201 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
202 ? CPUAttr.getValueAsString().str()
204 std::string FS = !FSAttr.hasAttribute(Attribute::None)
205 ? FSAttr.getValueAsString().str()
208 auto &I = SubtargetMap[CPU + FS];
210 // This needs to be done before we create a new subtarget since any
211 // creation will depend on the TM and the code generation flags on the
212 // function that reside in TargetOptions.
213 resetTargetOptions(F);
214 I = llvm::make_unique<PPCSubtarget>(
216 // FIXME: It would be good to have the subtarget additions here
217 // not necessary. Anything that turns them on/off (overrides) ends
218 // up being put at the end of the feature string, but the defaults
219 // shouldn't require adding them. Fixing this means pulling Feature64Bit
220 // out of most of the target cpus in the .td file and making it set only
221 // as part of initialization via the TargetTriple.
222 computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
227 //===----------------------------------------------------------------------===//
228 // Pass Pipeline Configuration
229 //===----------------------------------------------------------------------===//
232 /// PPC Code Generator Pass Configuration Options.
233 class PPCPassConfig : public TargetPassConfig {
235 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
236 : TargetPassConfig(TM, PM) {}
238 PPCTargetMachine &getPPCTargetMachine() const {
239 return getTM<PPCTargetMachine>();
242 void addIRPasses() override;
243 bool addPreISel() override;
244 bool addILPOpts() override;
245 bool addInstSelector() override;
246 void addMachineSSAOptimization() override;
247 void addPreRegAlloc() override;
248 void addPreSched2() override;
249 void addPreEmitPass() override;
253 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
254 return new PPCPassConfig(this, PM);
257 void PPCPassConfig::addIRPasses() {
258 addPass(createAtomicExpandPass(&getPPCTargetMachine()));
260 // For the BG/Q (or if explicitly requested), add explicit data prefetch
262 bool UsePrefetching =
263 Triple(TM->getTargetTriple()).getVendor() == Triple::BGQ &&
264 getOptLevel() != CodeGenOpt::None;
265 if (EnablePrefetch.getNumOccurrences() > 0)
266 UsePrefetching = EnablePrefetch;
268 addPass(createPPCLoopDataPrefetchPass());
270 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
271 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
272 // and lower a GEP with multiple indices to either arithmetic operations or
273 // multiple GEPs with single index.
274 addPass(createSeparateConstOffsetFromGEPPass(TM, true));
275 // Call EarlyCSE pass to find and remove subexpressions in the lowered
277 addPass(createEarlyCSEPass());
278 // Do loop invariant code motion in case part of the lowered result is
280 addPass(createLICMPass());
283 TargetPassConfig::addIRPasses();
286 bool PPCPassConfig::addPreISel() {
287 if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
288 addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
290 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
291 addPass(createPPCCTRLoops(getPPCTargetMachine()));
296 bool PPCPassConfig::addILPOpts() {
297 addPass(&EarlyIfConverterID);
301 bool PPCPassConfig::addInstSelector() {
302 // Install an instruction selector.
303 addPass(createPPCISelDag(getPPCTargetMachine()));
306 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
307 addPass(createPPCCTRLoopsVerify());
310 addPass(createPPCVSXCopyPass());
314 void PPCPassConfig::addMachineSSAOptimization() {
315 TargetPassConfig::addMachineSSAOptimization();
316 // For little endian, remove where possible the vector swap instructions
317 // introduced at code generation to normalize vector element order.
318 if (Triple(TM->getTargetTriple()).getArch() == Triple::ppc64le &&
319 !DisableVSXSwapRemoval)
320 addPass(createPPCVSXSwapRemovalPass());
323 void PPCPassConfig::addPreRegAlloc() {
324 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
325 insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
327 if (getPPCTargetMachine().getRelocationModel() == Reloc::PIC_)
328 addPass(createPPCTLSDynamicCallPass());
331 void PPCPassConfig::addPreSched2() {
332 if (getOptLevel() != CodeGenOpt::None)
333 addPass(&IfConverterID);
336 void PPCPassConfig::addPreEmitPass() {
337 if (getOptLevel() != CodeGenOpt::None)
338 addPass(createPPCEarlyReturnPass(), false);
339 // Must run branch selection immediately preceding the asm printer.
340 addPass(createPPCBranchSelectionPass(), false);
343 TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
344 return TargetIRAnalysis(
345 [this](Function &F) { return TargetTransformInfo(PPCTTIImpl(this, F)); });