1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
17 #include "PPCFrameLowering.h"
18 #include "PPCISelLowering.h"
19 #include "PPCInstrInfo.h"
20 #include "PPCSelectionDAGInfo.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "PPCGenSubtargetInfo.inc"
30 // GCC #defines PPC on Linux but we use it as our namespace name
37 // -m directive values.
66 class PPCSubtarget : public PPCGenSubtargetInfo {
68 /// TargetTriple - What processor and OS we're targeting.
71 /// stackAlignment - The minimum alignment known to hold of the stack frame on
72 /// entry to the function and which must be maintained by every function.
73 unsigned StackAlignment;
75 /// Selected instruction itineraries (one entry per itinerary class.)
76 InstrItineraryData InstrItins;
78 /// Which cpu directive was used.
79 unsigned DarwinDirective;
81 /// Used by the ISel to turn in optimizations for POWER4-derived architectures
95 bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
112 bool HasLazyResolverStubs;
115 bool HasInvariantFunctionDescriptors;
123 PPCFrameLowering FrameLowering;
124 PPCInstrInfo InstrInfo;
125 PPCTargetLowering TLInfo;
126 PPCSelectionDAGInfo TSInfo;
129 /// This constructor initializes the data members to match that
130 /// of the specified triple.
132 PPCSubtarget(const std::string &TT, const std::string &CPU,
133 const std::string &FS, const PPCTargetMachine &TM);
135 /// ParseSubtargetFeatures - Parses features string setting specified
136 /// subtarget options. Definition of function is auto generated by tblgen.
137 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
139 /// getStackAlignment - Returns the minimum alignment known to hold of the
140 /// stack frame on entry to the function and which must be maintained by every
141 /// function for this subtarget.
142 unsigned getStackAlignment() const { return StackAlignment; }
144 /// getDarwinDirective - Returns the -m directive specified for the cpu.
146 unsigned getDarwinDirective() const { return DarwinDirective; }
148 /// getInstrItins - Return the instruction itineraries based on subtarget
150 const InstrItineraryData *getInstrItineraryData() const override {
154 const PPCFrameLowering *getFrameLowering() const override {
155 return &FrameLowering;
157 const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
158 const PPCTargetLowering *getTargetLowering() const override {
161 const PPCSelectionDAGInfo *getSelectionDAGInfo() const override {
164 const PPCRegisterInfo *getRegisterInfo() const override {
165 return &getInstrInfo()->getRegisterInfo();
168 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
169 /// so that we can use initializer lists for subtarget initialization.
170 PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
173 void initializeEnvironment();
174 void initSubtargetFeatures(StringRef CPU, StringRef FS);
177 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
179 bool isPPC64() const { return IsPPC64; }
181 /// has64BitSupport - Return true if the selected CPU supports 64-bit
182 /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
183 bool has64BitSupport() const { return Has64BitSupport; }
185 /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
186 /// registers in 32-bit mode when possible. This can only true if
187 /// has64BitSupport() returns true.
188 bool use64BitRegs() const { return Use64BitRegs; }
190 /// useCRBits - Return true if we should store and manipulate i1 values in
191 /// the individual condition register bits.
192 bool useCRBits() const { return UseCRBits; }
194 /// hasLazyResolverStub - Return true if accesses to the specified global have
195 /// to go through a dyld lazy resolution stub. This means that an extra load
196 /// is required to get the address of the global.
197 bool hasLazyResolverStub(const GlobalValue *GV,
198 const TargetMachine &TM) const;
200 // isLittleEndian - True if generating little-endian code
201 bool isLittleEndian() const { return IsLittleEndian; }
203 // Specific obvious features.
204 bool hasFCPSGN() const { return HasFCPSGN; }
205 bool hasFSQRT() const { return HasFSQRT; }
206 bool hasFRE() const { return HasFRE; }
207 bool hasFRES() const { return HasFRES; }
208 bool hasFRSQRTE() const { return HasFRSQRTE; }
209 bool hasFRSQRTES() const { return HasFRSQRTES; }
210 bool hasRecipPrec() const { return HasRecipPrec; }
211 bool hasSTFIWX() const { return HasSTFIWX; }
212 bool hasLFIWAX() const { return HasLFIWAX; }
213 bool hasFPRND() const { return HasFPRND; }
214 bool hasFPCVT() const { return HasFPCVT; }
215 bool hasAltivec() const { return HasAltivec; }
216 bool hasSPE() const { return HasSPE; }
217 bool hasQPX() const { return HasQPX; }
218 bool hasVSX() const { return HasVSX; }
219 bool hasP8Vector() const { return HasP8Vector; }
220 bool hasP8Altivec() const { return HasP8Altivec; }
221 bool hasMFOCRF() const { return HasMFOCRF; }
222 bool hasISEL() const { return HasISEL; }
223 bool hasPOPCNTD() const { return HasPOPCNTD; }
224 bool hasCMPB() const { return HasCMPB; }
225 bool hasLDBRX() const { return HasLDBRX; }
226 bool isBookE() const { return IsBookE; }
227 bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
228 bool isPPC4xx() const { return IsPPC4xx; }
229 bool isPPC6xx() const { return IsPPC6xx; }
230 bool isE500() const { return IsE500; }
231 bool isDeprecatedMFTB() const { return DeprecatedMFTB; }
232 bool isDeprecatedDST() const { return DeprecatedDST; }
233 bool hasICBT() const { return HasICBT; }
234 bool hasInvariantFunctionDescriptors() const {
235 return HasInvariantFunctionDescriptors;
238 const Triple &getTargetTriple() const { return TargetTriple; }
240 /// isDarwin - True if this is any darwin platform.
241 bool isDarwin() const { return TargetTriple.isMacOSX(); }
242 /// isBGQ - True if this is a BG/Q platform.
243 bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
245 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
246 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
248 bool isDarwinABI() const { return isDarwin(); }
249 bool isSVR4ABI() const { return !isDarwin(); }
250 bool isELFv2ABI() const { return TargetABI == PPC_ABI_ELFv2; }
252 bool enableEarlyIfConversion() const override { return hasISEL(); }
254 // Scheduling customization.
255 bool enableMachineScheduler() const override;
256 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
257 bool enablePostMachineScheduler() const override;
258 AntiDepBreakMode getAntiDepBreakMode() const override;
259 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
261 void overrideSchedPolicy(MachineSchedPolicy &Policy,
264 unsigned NumRegionInstrs) const override;
265 bool useAA() const override;
267 bool enableSubRegLiveness() const override;
269 } // End llvm namespace