1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "PPCSubtarget.h"
16 #include "PPCRegisterInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineScheduler.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/IR/GlobalValue.h"
22 #include "llvm/Support/Host.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetMachine.h"
29 #define DEBUG_TYPE "ppc-subtarget"
31 #define GET_SUBTARGETINFO_TARGET_DESC
32 #define GET_SUBTARGETINFO_CTOR
33 #include "PPCGenSubtargetInfo.inc"
35 /// Return the datalayout string of a subtarget.
36 static std::string getDataLayoutString(const PPCSubtarget &ST) {
37 const Triple &T = ST.getTargetTriple();
41 // Most PPC* platforms are big endian, PPC64LE is little endian.
42 if (ST.isLittleEndian())
47 Ret += DataLayout::getManglingComponent(T);
49 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
51 if (!ST.isPPC64() || T.getOS() == Triple::Lv2)
54 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
55 // documentation are wrong; these are correct (i.e. "what gcc does").
56 if (ST.isPPC64() || ST.isSVR4ABI())
61 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
70 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
72 initializeEnvironment();
73 resetSubtargetFeatures(CPU, FS);
77 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
78 const std::string &FS, PPCTargetMachine &TM,
79 bool is64Bit, CodeGenOpt::Level OptLevel)
80 : PPCGenSubtargetInfo(TT, CPU, FS), IsPPC64(is64Bit), TargetTriple(TT),
81 OptLevel(OptLevel), TargetABI(PPC_ABI_UNKNOWN),
82 FrameLowering(initializeSubtargetDependencies(CPU, FS)),
83 DL(getDataLayoutString(*this)), InstrInfo(*this),
84 TLInfo(TM), TSInfo(&DL) {}
86 void PPCSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
87 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
88 Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
90 Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
93 !CPUAttr.hasAttribute(Attribute::None) ? CPUAttr.getValueAsString() : "";
95 !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
97 initializeEnvironment();
98 resetSubtargetFeatures(CPU, FS);
102 void PPCSubtarget::initializeEnvironment() {
104 DarwinDirective = PPC::DIR_NONE;
106 Has64BitSupport = false;
107 Use64BitRegs = false;
119 HasRecipPrec = false;
131 DeprecatedMFTB = false;
132 DeprecatedDST = false;
133 HasLazyResolverStubs = false;
136 void PPCSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
137 // Determine default and user specified characteristics
138 std::string CPUName = CPU;
141 #if (defined(__APPLE__) || defined(__linux__)) && \
142 (defined(__ppc__) || defined(__powerpc__))
143 if (CPUName == "generic")
144 CPUName = sys::getHostCPUName();
147 // Initialize scheduling itinerary for the specified CPU.
148 InstrItins = getInstrItineraryForCPU(CPUName);
150 // Make sure 64-bit features are available when CPUname is generic
151 std::string FullFS = FS;
153 // If we are generating code for ppc64, verify that options make sense.
155 Has64BitSupport = true;
156 // Silently force 64-bit register use on ppc64.
159 FullFS = "+64bit," + FullFS;
164 // At -O2 and above, track CR bits as individual registers.
165 if (OptLevel >= CodeGenOpt::Default) {
167 FullFS = "+crbits," + FullFS;
172 // Parse features string.
173 ParseSubtargetFeatures(CPUName, FullFS);
175 // If the user requested use of 64-bit regs, but the cpu selected doesn't
176 // support it, ignore.
177 if (use64BitRegs() && !has64BitSupport())
178 Use64BitRegs = false;
180 // Set up darwin-specific properties.
182 HasLazyResolverStubs = true;
184 // QPX requires a 32-byte aligned stack. Note that we need to do this if
185 // we're compiling for a BG/Q system regardless of whether or not QPX
186 // is enabled because external functions will assume this alignment.
187 if (hasQPX() || isBGQ())
190 // Determine endianness.
191 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
193 // FIXME: For now, we disable VSX in little-endian mode until endian
194 // issues in those instructions can be addressed.
198 // Determine default ABI.
199 if (TargetABI == PPC_ABI_UNKNOWN) {
200 if (!isDarwin() && IsPPC64) {
202 TargetABI = PPC_ABI_ELFv2;
204 TargetABI = PPC_ABI_ELFv1;
209 /// hasLazyResolverStub - Return true if accesses to the specified global have
210 /// to go through a dyld lazy resolution stub. This means that an extra load
211 /// is required to get the address of the global.
212 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
213 const TargetMachine &TM) const {
214 // We never have stubs if HasLazyResolverStubs=false or if in static mode.
215 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
217 // If symbol visibility is hidden, the extra load is not needed if
218 // the symbol is definitely defined in the current translation unit.
219 bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
220 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
222 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
223 GV->hasCommonLinkage() || isDecl;
226 // Embedded cores need aggressive scheduling (and some others also benefit).
227 static bool needsAggressiveScheduling(unsigned Directive) {
229 default: return false;
232 case PPC::DIR_E500mc:
240 bool PPCSubtarget::enableMachineScheduler() const {
241 // Enable MI scheduling for the embedded cores.
242 // FIXME: Enable this for all cores (some additional modeling
243 // may be necessary).
244 return needsAggressiveScheduling(DarwinDirective);
247 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
248 bool PPCSubtarget::enablePostMachineScheduler() const { return true; }
250 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
251 return TargetSubtargetInfo::ANTIDEP_ALL;
254 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
255 CriticalPathRCs.clear();
256 CriticalPathRCs.push_back(isPPC64() ?
257 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
260 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
263 unsigned NumRegionInstrs) const {
264 if (needsAggressiveScheduling(DarwinDirective)) {
265 Policy.OnlyTopDown = false;
266 Policy.OnlyBottomUp = false;
269 // Spilling is generally expensive on all PPC cores, so always enable
270 // register-pressure tracking.
271 Policy.ShouldTrackPressure = true;
274 bool PPCSubtarget::useAA() const {
275 // Use AA during code generation for the embedded cores.
276 return needsAggressiveScheduling(DarwinDirective);