1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "PPCSubtarget.h"
16 #include "PPCRegisterInfo.h"
17 #include "PPCTargetMachine.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineScheduler.h"
20 #include "llvm/IR/Attributes.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/IR/GlobalValue.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Host.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Target/TargetMachine.h"
31 #define DEBUG_TYPE "ppc-subtarget"
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #define GET_SUBTARGETINFO_CTOR
35 #include "PPCGenSubtargetInfo.inc"
37 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
38 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
40 static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned",
41 cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"),
44 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
46 initializeEnvironment();
47 initSubtargetFeatures(CPU, FS);
51 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
52 const std::string &FS, const PPCTargetMachine &TM)
53 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
54 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
55 TargetTriple.getArch() == Triple::ppc64le),
56 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
57 InstrInfo(*this), TLInfo(TM, *this), TSInfo(TM.getDataLayout()) {}
59 void PPCSubtarget::initializeEnvironment() {
61 DarwinDirective = PPC::DIR_NONE;
63 Has64BitSupport = false;
93 DeprecatedMFTB = false;
94 DeprecatedDST = false;
95 HasLazyResolverStubs = false;
97 HasInvariantFunctionDescriptors = false;
98 HasPartwordAtomics = false;
99 IsQPXStackUnaligned = false;
103 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
104 // Determine default and user specified characteristics
105 std::string CPUName = CPU;
106 if (CPUName.empty()) {
107 // If cross-compiling with -march=ppc64le without -mcpu
108 if (TargetTriple.getArch() == Triple::ppc64le)
113 #if (defined(__APPLE__) || defined(__linux__)) && \
114 (defined(__ppc__) || defined(__powerpc__))
115 if (CPUName == "generic")
116 CPUName = sys::getHostCPUName();
119 // Initialize scheduling itinerary for the specified CPU.
120 InstrItins = getInstrItineraryForCPU(CPUName);
122 // Parse features string.
123 ParseSubtargetFeatures(CPUName, FS);
125 // If the user requested use of 64-bit regs, but the cpu selected doesn't
126 // support it, ignore.
127 if (IsPPC64 && has64BitSupport())
130 // Set up darwin-specific properties.
132 HasLazyResolverStubs = true;
134 // QPX requires a 32-byte aligned stack. Note that we need to do this if
135 // we're compiling for a BG/Q system regardless of whether or not QPX
136 // is enabled because external functions will assume this alignment.
137 IsQPXStackUnaligned = QPXStackUnaligned;
138 StackAlignment = getPlatformStackAlignment();
140 // Determine endianness.
141 // FIXME: Part of the TargetMachine.
142 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
145 /// hasLazyResolverStub - Return true if accesses to the specified global have
146 /// to go through a dyld lazy resolution stub. This means that an extra load
147 /// is required to get the address of the global.
148 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const {
149 // We never have stubs if HasLazyResolverStubs=false or if in static mode.
150 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
152 bool isDecl = GV->isDeclaration();
153 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
155 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
156 GV->hasCommonLinkage() || isDecl;
159 // Embedded cores need aggressive scheduling (and some others also benefit).
160 static bool needsAggressiveScheduling(unsigned Directive) {
162 default: return false;
165 case PPC::DIR_E500mc:
173 bool PPCSubtarget::enableMachineScheduler() const {
174 // Enable MI scheduling for the embedded cores.
175 // FIXME: Enable this for all cores (some additional modeling
176 // may be necessary).
177 return needsAggressiveScheduling(DarwinDirective);
180 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
181 bool PPCSubtarget::enablePostMachineScheduler() const { return true; }
183 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
184 return TargetSubtargetInfo::ANTIDEP_ALL;
187 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
188 CriticalPathRCs.clear();
189 CriticalPathRCs.push_back(isPPC64() ?
190 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
193 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
196 unsigned NumRegionInstrs) const {
197 if (needsAggressiveScheduling(DarwinDirective)) {
198 Policy.OnlyTopDown = false;
199 Policy.OnlyBottomUp = false;
202 // Spilling is generally expensive on all PPC cores, so always enable
203 // register-pressure tracking.
204 Policy.ShouldTrackPressure = true;
207 bool PPCSubtarget::useAA() const {
208 // Use AA during code generation for the embedded cores.
209 return needsAggressiveScheduling(DarwinDirective);
212 bool PPCSubtarget::enableSubRegLiveness() const {
213 return UseSubRegLiveness;
216 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
217 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }