1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "PPCSubtarget.h"
16 #include "PPCRegisterInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineScheduler.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/IR/GlobalValue.h"
22 #include "llvm/Support/Host.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetMachine.h"
29 #define DEBUG_TYPE "ppc-subtarget"
31 #define GET_SUBTARGETINFO_TARGET_DESC
32 #define GET_SUBTARGETINFO_CTOR
33 #include "PPCGenSubtargetInfo.inc"
35 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
36 const std::string &FS, bool is64Bit,
37 CodeGenOpt::Level OptLevel)
38 : PPCGenSubtargetInfo(TT, CPU, FS)
41 initializeEnvironment();
43 std::string FullFS = FS;
45 // At -O2 and above, track CR bits as individual registers.
46 if (OptLevel >= CodeGenOpt::Default) {
48 FullFS = "+crbits," + FullFS;
53 resetSubtargetFeatures(CPU, FullFS);
56 /// SetJITMode - This is called to inform the subtarget info that we are
57 /// producing code for the JIT.
58 void PPCSubtarget::SetJITMode() {
59 // JIT mode doesn't want lazy resolver stubs, it knows exactly where
60 // everything is. This matters for PPC64, which codegens in PIC mode without
62 HasLazyResolverStubs = false;
64 // Calls to external functions need to use indirect calls
65 IsJITCodeModel = true;
68 void PPCSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
69 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
70 Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
72 Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
75 !CPUAttr.hasAttribute(Attribute::None) ? CPUAttr.getValueAsString() : "";
77 !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
79 initializeEnvironment();
80 resetSubtargetFeatures(CPU, FS);
84 void PPCSubtarget::initializeEnvironment() {
86 DarwinDirective = PPC::DIR_NONE;
88 Has64BitSupport = false;
100 HasRecipPrec = false;
109 DeprecatedMFTB = false;
110 DeprecatedDST = false;
111 HasLazyResolverStubs = false;
112 IsJITCodeModel = false;
115 void PPCSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
116 // Determine default and user specified characteristics
117 std::string CPUName = CPU;
120 #if (defined(__APPLE__) || defined(__linux__)) && \
121 (defined(__ppc__) || defined(__powerpc__))
122 if (CPUName == "generic")
123 CPUName = sys::getHostCPUName();
126 // Initialize scheduling itinerary for the specified CPU.
127 InstrItins = getInstrItineraryForCPU(CPUName);
129 // Make sure 64-bit features are available when CPUname is generic
130 std::string FullFS = FS;
132 // If we are generating code for ppc64, verify that options make sense.
134 Has64BitSupport = true;
135 // Silently force 64-bit register use on ppc64.
138 FullFS = "+64bit," + FullFS;
143 // Parse features string.
144 ParseSubtargetFeatures(CPUName, FullFS);
146 // If the user requested use of 64-bit regs, but the cpu selected doesn't
147 // support it, ignore.
148 if (use64BitRegs() && !has64BitSupport())
149 Use64BitRegs = false;
151 // Set up darwin-specific properties.
153 HasLazyResolverStubs = true;
155 // QPX requires a 32-byte aligned stack. Note that we need to do this if
156 // we're compiling for a BG/Q system regardless of whether or not QPX
157 // is enabled because external functions will assume this alignment.
158 if (hasQPX() || isBGQ())
161 // Determine endianness.
162 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
165 /// hasLazyResolverStub - Return true if accesses to the specified global have
166 /// to go through a dyld lazy resolution stub. This means that an extra load
167 /// is required to get the address of the global.
168 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
169 const TargetMachine &TM) const {
170 // We never have stubs if HasLazyResolverStubs=false or if in static mode.
171 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
173 // If symbol visibility is hidden, the extra load is not needed if
174 // the symbol is definitely defined in the current translation unit.
175 bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
176 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
178 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
179 GV->hasCommonLinkage() || isDecl;
182 bool PPCSubtarget::enablePostRAScheduler(
183 CodeGenOpt::Level OptLevel,
184 TargetSubtargetInfo::AntiDepBreakMode& Mode,
185 RegClassVector& CriticalPathRCs) const {
186 Mode = TargetSubtargetInfo::ANTIDEP_ALL;
188 CriticalPathRCs.clear();
191 CriticalPathRCs.push_back(&PPC::G8RCRegClass);
193 CriticalPathRCs.push_back(&PPC::GPRCRegClass);
195 return OptLevel >= CodeGenOpt::Default;
198 // Embedded cores need aggressive scheduling (and some others also benefit).
199 static bool needsAggressiveScheduling(unsigned Directive) {
201 default: return false;
204 case PPC::DIR_E500mc:
211 bool PPCSubtarget::enableMachineScheduler() const {
212 // Enable MI scheduling for the embedded cores.
213 // FIXME: Enable this for all cores (some additional modeling
214 // may be necessary).
215 return needsAggressiveScheduling(DarwinDirective);
218 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
221 unsigned NumRegionInstrs) const {
222 if (needsAggressiveScheduling(DarwinDirective)) {
223 Policy.OnlyTopDown = false;
224 Policy.OnlyBottomUp = false;
227 // Spilling is generally expensive on all PPC cores, so always enable
228 // register-pressure tracking.
229 Policy.ShouldTrackPressure = true;
232 bool PPCSubtarget::useAA() const {
233 // Use AA during code generation for the embedded cores.
234 return needsAggressiveScheduling(DarwinDirective);