1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "PPCSubtarget.h"
16 #include "PPCRegisterInfo.h"
17 #include "PPCTargetMachine.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineScheduler.h"
20 #include "llvm/IR/Attributes.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/IR/GlobalValue.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Host.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Target/TargetMachine.h"
31 #define DEBUG_TYPE "ppc-subtarget"
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #define GET_SUBTARGETINFO_CTOR
35 #include "PPCGenSubtargetInfo.inc"
37 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
38 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
40 static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned",
41 cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"),
44 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
46 initializeEnvironment();
47 initSubtargetFeatures(CPU, FS);
51 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
52 const std::string &FS, const PPCTargetMachine &TM)
53 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
54 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
55 TargetTriple.getArch() == Triple::ppc64le),
56 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
57 InstrInfo(*this), TLInfo(TM, *this), TSInfo(TM.getDataLayout()) {}
59 void PPCSubtarget::initializeEnvironment() {
61 DarwinDirective = PPC::DIR_NONE;
63 Has64BitSupport = false;
93 DeprecatedMFTB = false;
94 DeprecatedDST = false;
95 HasLazyResolverStubs = false;
97 HasInvariantFunctionDescriptors = false;
98 HasPartwordAtomics = false;
99 IsQPXStackUnaligned = false;
102 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
103 // Determine default and user specified characteristics
104 std::string CPUName = CPU;
105 if (CPUName.empty()) {
106 // If cross-compiling with -march=ppc64le without -mcpu
107 if (TargetTriple.getArch() == Triple::ppc64le)
112 #if (defined(__APPLE__) || defined(__linux__)) && \
113 (defined(__ppc__) || defined(__powerpc__))
114 if (CPUName == "generic")
115 CPUName = sys::getHostCPUName();
118 // Initialize scheduling itinerary for the specified CPU.
119 InstrItins = getInstrItineraryForCPU(CPUName);
121 // Parse features string.
122 ParseSubtargetFeatures(CPUName, FS);
124 // If the user requested use of 64-bit regs, but the cpu selected doesn't
125 // support it, ignore.
126 if (IsPPC64 && has64BitSupport())
129 // Set up darwin-specific properties.
131 HasLazyResolverStubs = true;
133 // QPX requires a 32-byte aligned stack. Note that we need to do this if
134 // we're compiling for a BG/Q system regardless of whether or not QPX
135 // is enabled because external functions will assume this alignment.
136 IsQPXStackUnaligned = QPXStackUnaligned;
137 StackAlignment = getPlatformStackAlignment();
139 // Determine endianness.
140 // FIXME: Part of the TargetMachine.
141 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
144 /// hasLazyResolverStub - Return true if accesses to the specified global have
145 /// to go through a dyld lazy resolution stub. This means that an extra load
146 /// is required to get the address of the global.
147 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const {
148 // We never have stubs if HasLazyResolverStubs=false or if in static mode.
149 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
151 bool isDecl = GV->isDeclaration();
152 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
154 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
155 GV->hasCommonLinkage() || isDecl;
158 // Embedded cores need aggressive scheduling (and some others also benefit).
159 static bool needsAggressiveScheduling(unsigned Directive) {
161 default: return false;
164 case PPC::DIR_E500mc:
172 bool PPCSubtarget::enableMachineScheduler() const {
173 // Enable MI scheduling for the embedded cores.
174 // FIXME: Enable this for all cores (some additional modeling
175 // may be necessary).
176 return needsAggressiveScheduling(DarwinDirective);
179 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
180 bool PPCSubtarget::enablePostMachineScheduler() const { return true; }
182 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
183 return TargetSubtargetInfo::ANTIDEP_ALL;
186 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
187 CriticalPathRCs.clear();
188 CriticalPathRCs.push_back(isPPC64() ?
189 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
192 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
195 unsigned NumRegionInstrs) const {
196 if (needsAggressiveScheduling(DarwinDirective)) {
197 Policy.OnlyTopDown = false;
198 Policy.OnlyBottomUp = false;
201 // Spilling is generally expensive on all PPC cores, so always enable
202 // register-pressure tracking.
203 Policy.ShouldTrackPressure = true;
206 bool PPCSubtarget::useAA() const {
207 // Use AA during code generation for the embedded cores.
208 return needsAggressiveScheduling(DarwinDirective);
211 bool PPCSubtarget::enableSubRegLiveness() const {
212 return UseSubRegLiveness;
215 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
216 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }