1 //===- PPCScheduleG3.td - PPC G3 Scheduling Definitions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the G3 (750) processor.
12 //===----------------------------------------------------------------------===//
15 def G3Itineraries : ProcessorItineraries<
16 [IU1, IU2, FPU1, BPU, SRU, SLU], [], [
17 InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>,
18 InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>,
19 InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>,
20 InstrItinData<IntMFFS , [InstrStage<1, [FPU1]>]>,
21 InstrItinData<IntMTFSB0 , [InstrStage<3, [FPU1]>]>,
22 InstrItinData<IntMulHW , [InstrStage<5, [IU1]>]>,
23 InstrItinData<IntMulHWU , [InstrStage<6, [IU1]>]>,
24 InstrItinData<IntMulLI , [InstrStage<3, [IU1]>]>,
25 InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2]>]>,
26 InstrItinData<IntShift , [InstrStage<1, [IU1, IU2]>]>,
27 InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2]>]>,
28 InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
29 InstrItinData<BrCR , [InstrStage<1, [SRU]>]>,
30 InstrItinData<BrMCR , [InstrStage<1, [SRU]>]>,
31 InstrItinData<BrMCRX , [InstrStage<1, [SRU]>]>,
32 InstrItinData<LdStDCBA , [InstrStage<2, [SLU]>]>,
33 InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
34 InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>,
35 InstrItinData<LdStGeneral , [InstrStage<2, [SLU]>]>,
36 InstrItinData<LdStICBI , [InstrStage<3, [SLU]>]>,
37 InstrItinData<LdStUX , [InstrStage<2, [SLU]>]>,
38 InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>,
39 InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>,
40 InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>,
41 InstrItinData<LdStLMW , [InstrStage<34, [SLU]>]>,
42 InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
43 InstrItinData<LdStSTWCX , [InstrStage<8, [SLU]>]>,
44 InstrItinData<LdStSync , [InstrStage<3, [SLU]>]>,
45 InstrItinData<SprISYNC , [InstrStage<2, [SRU]>]>,
46 InstrItinData<SprMFSR , [InstrStage<3, [SRU]>]>,
47 InstrItinData<SprMTMSR , [InstrStage<1, [SRU]>]>,
48 InstrItinData<SprMTSR , [InstrStage<2, [SRU]>]>,
49 InstrItinData<SprTLBSYNC , [InstrStage<3, [SRU]>]>,
50 InstrItinData<SprMFCR , [InstrStage<1, [SRU]>]>,
51 InstrItinData<SprMFMSR , [InstrStage<1, [SRU]>]>,
52 InstrItinData<SprMFSPR , [InstrStage<3, [SRU]>]>,
53 InstrItinData<SprMFTB , [InstrStage<3, [SRU]>]>,
54 InstrItinData<SprMTSPR , [InstrStage<2, [SRU]>]>,
55 InstrItinData<SprMTSRIN , [InstrStage<2, [SRU]>]>,
56 InstrItinData<SprRFI , [InstrStage<2, [SRU]>]>,
57 InstrItinData<SprSC , [InstrStage<2, [SRU]>]>,
58 InstrItinData<FPGeneral , [InstrStage<1, [FPU1]>]>,
59 InstrItinData<FPCompare , [InstrStage<1, [FPU1]>]>,
60 InstrItinData<FPDivD , [InstrStage<31, [FPU1]>]>,
61 InstrItinData<FPDivS , [InstrStage<17, [FPU1]>]>,
62 InstrItinData<FPFused , [InstrStage<2, [FPU1]>]>,
63 InstrItinData<FPRes , [InstrStage<10, [FPU1]>]>