lib/Target/PowerPC/PPCScheduleE500mc.td

   1 //===-- PPCScheduleE500mc.td - e500mc Scheduling Defs ------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the Freescale e500mc 32-bit
  11 // Power processor.
  12 //
  13 // All information is derived from the "e500mc Core Reference Manual",
  14 // Freescale Document Number E500MCRM, Rev. 1, 03/2012.
  15 //
  16 //===----------------------------------------------------------------------===//
  17 // Relevant functional units in the Freescale e500mc core:
  18 //
  19 //  * Decode & Dispatch
  20 //    Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
  21 //    queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
  22 def DIS0 : FuncUnit; // Dispatch stage - insn 1
  23 def DIS1 : FuncUnit; // Dispatch stage - insn 2
  24
  25 //  * Execute
  26 //    6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
  27 //    Some instructions can only execute in SFX0 but not SFX1.
  28 //    The CFX has a bypass path, allowing non-divide instructions to execute
  29 //    while a divide instruction is executed.
  30 def SFX0  : FuncUnit; // Simple unit 0
  31 def SFX1  : FuncUnit; // Simple unit 1
  32 def BU    : FuncUnit; // Branch unit
  33 def CFX_DivBypass
  34           : FuncUnit; // CFX divide bypass path
  35 def CFX_0 : FuncUnit; // CFX pipeline
  36 def LSU_0 : FuncUnit; // LSU pipeline
  37 def FPU_0 : FuncUnit; // FPU pipeline
  38
  39 def CR_Bypass : Bypass;
  40
  41 def PPCE500mcItineraries : ProcessorItineraries<
  42   [DIS0, DIS1, SFX0, SFX1, BU, CFX_DivBypass, CFX_0, LSU_0, FPU_0],
  43   [CR_Bypass, GPR_Bypass, FPR_Bypass], [
  44   InstrItinData<IIC_IntSimple,   [InstrStage<1, [DIS0, DIS1], 0>,
  45                                   InstrStage<1, [SFX0, SFX1]>],
  46                                  [4, 1, 1], // Latency = 1
  47                                  [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  48   InstrItinData<IIC_IntGeneral,  [InstrStage<1, [DIS0, DIS1], 0>,
  49                                   InstrStage<1, [SFX0, SFX1]>],
  50                                  [4, 1, 1], // Latency = 1
  51                                  [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  52   InstrItinData<IIC_IntCompare,  [InstrStage<1, [DIS0, DIS1], 0>,
  53                                   InstrStage<1, [SFX0, SFX1]>],
  54                                  [5, 1, 1], // Latency = 1 or 2
  55                                  [CR_Bypass, GPR_Bypass, GPR_Bypass]>,
  56   InstrItinData<IIC_IntDivW,     [InstrStage<1, [DIS0, DIS1], 0>,
  57                                   InstrStage<1, [CFX_0], 0>,
  58                                   InstrStage<14, [CFX_DivBypass]>],
  59                                  [17, 1, 1], // Latency=4..35, Repeat= 4..35
  60                                  [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  61   InstrItinData<IIC_IntMFFS,     [InstrStage<1, [DIS0, DIS1], 0>,
  62                                   InstrStage<8, [FPU_0]>],
  63                                  [11], // Latency = 8
  64                                  [FPR_Bypass]>,
  65   InstrItinData<IIC_IntMTFSB0,   [InstrStage<1, [DIS0, DIS1], 0>,
  66                                   InstrStage<8, [FPU_0]>],
  67                                  [11, 1, 1], // Latency = 8
  68                                  [NoBypass, NoBypass, NoBypass]>,
  69   InstrItinData<IIC_IntMulHW,    [InstrStage<1, [DIS0, DIS1], 0>,
  70                                   InstrStage<1, [CFX_0]>],
  71                                  [7, 1, 1], // Latency = 4, Repeat rate = 1
  72                                  [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  73   InstrItinData<IIC_IntMulHWU,   [InstrStage<1, [DIS0, DIS1], 0>,
  74                                   InstrStage<1, [CFX_0]>],
  75                                  [7, 1, 1], // Latency = 4, Repeat rate = 1
  76                                  [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  77   InstrItinData<IIC_IntMulLI,    [InstrStage<1, [DIS0, DIS1], 0>,
  78                                   InstrStage<1, [CFX_0]>],
  79                                  [7, 1, 1], // Latency = 4, Repeat rate = 1
  80                                  [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  81   InstrItinData<IIC_IntRotate,   [InstrStage<1, [DIS0, DIS1], 0>,
  82                                   InstrStage<1, [SFX0, SFX1]>],
  83                                  [4, 1, 1], // Latency = 1
  84                                  [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  85   InstrItinData<IIC_IntShift,    [InstrStage<1, [DIS0, DIS1], 0>,
  86                                   InstrStage<1, [SFX0, SFX1]>],
  87                                  [4, 1, 1], // Latency = 1
  88                                  [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  89   InstrItinData<IIC_IntTrapW,    [InstrStage<1, [DIS0, DIS1], 0>,
  90                                   InstrStage<2, [SFX0]>],
  91                                  [5, 1], // Latency = 2, Repeat rate = 2
  92                                  [GPR_Bypass, GPR_Bypass]>,
  93   InstrItinData<IIC_BrB,         [InstrStage<1, [DIS0, DIS1], 0>,
  94                                   InstrStage<1, [BU]>],
  95                                  [4, 1], // Latency = 1
  96                                  [NoBypass, GPR_Bypass]>,
  97   InstrItinData<IIC_BrCR,        [InstrStage<1, [DIS0, DIS1], 0>,
  98                                   InstrStage<1, [BU]>],
  99                                  [4, 1, 1], // Latency = 1
 100                                  [CR_Bypass, CR_Bypass, CR_Bypass]>,
 101   InstrItinData<IIC_BrMCR,       [InstrStage<1, [DIS0, DIS1], 0>,
 102                                   InstrStage<1, [BU]>],
 103                                  [4, 1], // Latency = 1
 104                                  [CR_Bypass, CR_Bypass]>,
 105   InstrItinData<IIC_BrMCRX,      [InstrStage<1, [DIS0, DIS1], 0>,
 106                                   InstrStage<1, [SFX0, SFX1]>],
 107                                  [4, 1, 1], // Latency = 1
 108                                  [CR_Bypass, GPR_Bypass]>,
 109   InstrItinData<IIC_LdStDCBA,    [InstrStage<1, [DIS0, DIS1], 0>,
 110                                   InstrStage<1, [LSU_0]>],
 111                                  [6, 1], // Latency = 3, Repeat rate = 1
 112                                  [GPR_Bypass, GPR_Bypass]>,
 113   InstrItinData<IIC_LdStDCBF,    [InstrStage<1, [DIS0, DIS1], 0>,
 114                                   InstrStage<1, [LSU_0]>],
 115                                  [6, 1], // Latency = 3
 116                                  [GPR_Bypass, GPR_Bypass]>,
 117   InstrItinData<IIC_LdStDCBI,    [InstrStage<1, [DIS0, DIS1], 0>,
 118                                   InstrStage<1, [LSU_0]>],
 119                                  [6, 1], // Latency = 3
 120                                  [GPR_Bypass, GPR_Bypass]>,
 121   InstrItinData<IIC_LdStLoad,    [InstrStage<1, [DIS0, DIS1], 0>,
 122                                   InstrStage<1, [LSU_0]>],
 123                                  [6, 1], // Latency = 3
 124                                  [GPR_Bypass, GPR_Bypass]>,
 125   InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [DIS0, DIS1], 0>,
 126                                   InstrStage<1, [SFX0, SFX1], 0>,
 127                                   InstrStage<1, [LSU_0]>],
 128                                  [6, 1], // Latency = 3
 129                                  [GPR_Bypass, GPR_Bypass],
 130                                  2>, // 2 micro-ops
 131   InstrItinData<IIC_LdStStore,   [InstrStage<1, [DIS0, DIS1], 0>,
 132                                   InstrStage<1, [LSU_0]>],
 133                                  [6, 1], // Latency = 3
 134                                  [NoBypass, GPR_Bypass]>,
 135   InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [DIS0, DIS1], 0>,
 136                                   InstrStage<1, [SFX0, SFX1], 0>,
 137                                   InstrStage<1, [LSU_0]>],
 138                                  [6, 1], // Latency = 3
 139                                  [NoBypass, GPR_Bypass],
 140                                  2>, // 2 micro-ops
 141   InstrItinData<IIC_LdStICBI,    [InstrStage<1, [DIS0, DIS1], 0>,
 142                                   InstrStage<1, [LSU_0]>],
 143                                  [6, 1], // Latency = 3
 144                                  [NoBypass, GPR_Bypass]>,
 145   InstrItinData<IIC_LdStSTFD,    [InstrStage<1, [DIS0, DIS1], 0>,
 146                                   InstrStage<1, [LSU_0]>],
 147                                  [6, 1, 1], // Latency = 3
 148                                  [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 149   InstrItinData<IIC_LdStSTFDU,   [InstrStage<1, [DIS0, DIS1], 0>,
 150                                   InstrStage<1, [SFX0, SFX1], 0>,
 151                                   InstrStage<1, [LSU_0]>],
 152                                  [6, 1, 1], // Latency = 3
 153                                  [GPR_Bypass, GPR_Bypass, GPR_Bypass],
 154                                  2>, // 2 micro-ops
 155   InstrItinData<IIC_LdStLFD,     [InstrStage<1, [DIS0, DIS1], 0>,
 156                                   InstrStage<1, [LSU_0]>],
 157                                  [7, 1, 1], // Latency = 4
 158                                  [FPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 159   InstrItinData<IIC_LdStLFDU,    [InstrStage<1, [DIS0, DIS1], 0>,
 160                                   InstrStage<1, [SFX0, SFX1], 0>,
 161                                   InstrStage<1, [LSU_0]>],
 162                                  [7, 1, 1], // Latency = 4
 163                                  [FPR_Bypass, GPR_Bypass, GPR_Bypass],
 164                                  2>, // 2 micro-ops
 165   InstrItinData<IIC_LdStLHA,     [InstrStage<1, [DIS0, DIS1], 0>,
 166                                   InstrStage<1, [LSU_0]>],
 167                                  [6, 1], // Latency = 3
 168                                  [GPR_Bypass, GPR_Bypass]>,
 169   InstrItinData<IIC_LdStLHAU,    [InstrStage<1, [DIS0, DIS1], 0>,
 170                                   InstrStage<1, [SFX0, SFX1], 0>,
 171                                   InstrStage<1, [LSU_0]>],
 172                                  [6, 1], // Latency = 3
 173                                  [GPR_Bypass, GPR_Bypass]>,
 174   InstrItinData<IIC_LdStLMW,     [InstrStage<1, [DIS0, DIS1], 0>,
 175                                   InstrStage<1, [LSU_0]>],
 176                                  [7, 1], // Latency = r+3
 177                                  [NoBypass, GPR_Bypass]>,
 178   InstrItinData<IIC_LdStLWARX,   [InstrStage<1, [DIS0, DIS1], 0>,
 179                                   InstrStage<3, [LSU_0]>],
 180                                  [6, 1, 1], // Latency = 3, Repeat rate = 3
 181                                  [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 182   InstrItinData<IIC_LdStSTWCX,   [InstrStage<1, [DIS0, DIS1], 0>,
 183                                   InstrStage<1, [LSU_0]>],
 184                                  [6, 1], // Latency = 3
 185                                  [NoBypass, GPR_Bypass]>,
 186   InstrItinData<IIC_LdStSync,    [InstrStage<1, [DIS0, DIS1], 0>,
 187                                   InstrStage<1, [LSU_0]>]>,
 188   InstrItinData<IIC_SprMFSR,     [InstrStage<1, [DIS0, DIS1], 0>,
 189                                   InstrStage<4, [SFX0]>],
 190                                  [7, 1],
 191                                  [GPR_Bypass, GPR_Bypass]>,
 192   InstrItinData<IIC_SprMTMSR,    [InstrStage<1, [DIS0, DIS1], 0>,
 193                                   InstrStage<2, [SFX0, SFX1]>],
 194                                  [5, 1], // Latency = 2, Repeat rate = 4
 195                                  [GPR_Bypass, GPR_Bypass]>,
 196   InstrItinData<IIC_SprMTSR,     [InstrStage<1, [DIS0, DIS1], 0>,
 197                                   InstrStage<1, [SFX0]>],
 198                                  [5, 1],
 199                                  [NoBypass, GPR_Bypass]>,
 200   InstrItinData<IIC_SprTLBSYNC,  [InstrStage<1, [DIS0, DIS1], 0>,
 201                                   InstrStage<1, [LSU_0], 0>]>,
 202   InstrItinData<IIC_SprMFCR,     [InstrStage<1, [DIS0, DIS1], 0>,
 203                                   InstrStage<5, [SFX0]>],
 204                                  [8, 1],
 205                                  [GPR_Bypass, CR_Bypass]>,
 206   InstrItinData<IIC_SprMFMSR,    [InstrStage<1, [DIS0, DIS1], 0>,
 207                                   InstrStage<4, [SFX0]>],
 208                                  [7, 1], // Latency = 4, Repeat rate = 4
 209                                  [GPR_Bypass, GPR_Bypass]>,
 210   InstrItinData<IIC_SprMFSPR,    [InstrStage<1, [DIS0, DIS1], 0>,
 211                                   InstrStage<1, [SFX0, SFX1]>],
 212                                  [4, 1], // Latency = 1, Repeat rate = 1
 213                                  [GPR_Bypass, CR_Bypass]>,
 214   InstrItinData<IIC_SprMFTB,     [InstrStage<1, [DIS0, DIS1], 0>,
 215                                   InstrStage<4, [SFX0]>],
 216                                  [7, 1], // Latency = 4, Repeat rate = 4
 217                                  [NoBypass, GPR_Bypass]>,
 218   InstrItinData<IIC_SprMTSPR,    [InstrStage<1, [DIS0, DIS1], 0>,
 219                                   InstrStage<1, [SFX0, SFX1]>],
 220                                  [4, 1], // Latency = 1, Repeat rate = 1
 221                                  [CR_Bypass, GPR_Bypass]>,
 222   InstrItinData<IIC_SprMTSRIN,   [InstrStage<1, [DIS0, DIS1], 0>,
 223                                   InstrStage<1, [SFX0]>],
 224                                  [4, 1],
 225                                  [NoBypass, GPR_Bypass]>,
 226   InstrItinData<IIC_FPGeneral,   [InstrStage<1, [DIS0, DIS1], 0>,
 227                                   InstrStage<2, [FPU_0]>],
 228                                  [11, 1, 1], // Latency = 8, Repeat rate = 2
 229                                  [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 230   InstrItinData<IIC_FPAddSub,    [InstrStage<1, [DIS0, DIS1], 0>,
 231                                   InstrStage<4, [FPU_0]>],
 232                                  [13, 1, 1], // Latency = 10, Repeat rate = 4
 233                                  [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 234   InstrItinData<IIC_FPCompare,   [InstrStage<1, [DIS0, DIS1], 0>,
 235                                   InstrStage<2, [FPU_0]>],
 236                                  [11, 1, 1], // Latency = 8, Repeat rate = 2
 237                                  [CR_Bypass, FPR_Bypass, FPR_Bypass]>,
 238   InstrItinData<IIC_FPDivD,      [InstrStage<1, [DIS0, DIS1], 0>,
 239                                   InstrStage<68, [FPU_0]>],
 240                                  [71, 1, 1], // Latency = 68, Repeat rate = 68
 241                                  [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 242   InstrItinData<IIC_FPDivS,      [InstrStage<1, [DIS0, DIS1], 0>,
 243                                   InstrStage<38, [FPU_0]>],
 244                                  [41, 1, 1], // Latency = 38, Repeat rate = 38
 245                                  [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 246   InstrItinData<IIC_FPFused,     [InstrStage<1, [DIS0, DIS1], 0>,
 247                                   InstrStage<4, [FPU_0]>],
 248                                  [13, 1, 1, 1], // Latency = 10, Repeat rate = 4
 249                                  [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 250   InstrItinData<IIC_FPRes,       [InstrStage<1, [DIS0, DIS1], 0>,
 251                                   InstrStage<38, [FPU_0]>],
 252                                  [41, 1], // Latency = 38, Repeat rate = 38
 253                                  [FPR_Bypass, FPR_Bypass]>
 254 ]>;
 255
 256 // ===---------------------------------------------------------------------===//
 257 // e500mc machine model for scheduling and other instruction cost heuristics.
 258
 259 def PPCE500mcModel : SchedMachineModel {
 260   let IssueWidth = 2;  // 2 micro-ops are dispatched per cycle.
 261   let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
 262   let LoadLatency = 5; // Optimistic load latency assuming bypass.
 263                        // This is overriden by OperandCycles if the
 264                        // Itineraries are queried instead.
 265
 266   let Itineraries = PPCE500mcItineraries;
 267 }