1 //===-- PPCRegisterInfo.td - The PowerPC Register File -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 let Namespace = "PPC" in {
14 def sub_lt : SubRegIndex<1>;
15 def sub_gt : SubRegIndex<1, 1>;
16 def sub_eq : SubRegIndex<1, 2>;
17 def sub_un : SubRegIndex<1, 3>;
18 def sub_32 : SubRegIndex<32>;
19 def sub_64 : SubRegIndex<64>;
20 def sub_128 : SubRegIndex<128>;
24 class PPCReg<string n> : Register<n> {
25 let Namespace = "PPC";
28 // We identify all our registers with a 5-bit ID, for consistency's sake.
30 // GPR - One of the 32 32-bit general-purpose registers
31 class GPR<bits<5> num, string n> : PPCReg<n> {
32 let HWEncoding{4-0} = num;
35 // GP8 - One of the 32 64-bit general-purpose registers
36 class GP8<GPR SubReg, string n> : PPCReg<n> {
37 let HWEncoding = SubReg.HWEncoding;
38 let SubRegs = [SubReg];
39 let SubRegIndices = [sub_32];
42 // SPR - One of the 32-bit special-purpose registers
43 class SPR<bits<10> num, string n> : PPCReg<n> {
44 let HWEncoding{9-0} = num;
47 // FPR - One of the 32 64-bit floating-point registers
48 class FPR<bits<5> num, string n> : PPCReg<n> {
49 let HWEncoding{4-0} = num;
52 // VF - One of the 32 64-bit floating-point subregisters of the vector
53 // registers (used by VSX).
54 class VF<bits<5> num, string n> : PPCReg<n> {
55 let HWEncoding{4-0} = num;
56 let HWEncoding{5} = 1;
59 // VR - One of the 32 128-bit vector registers
60 class VR<VF SubReg, string n> : PPCReg<n> {
61 let HWEncoding{4-0} = SubReg.HWEncoding{4-0};
62 let HWEncoding{5} = 0;
63 let SubRegs = [SubReg];
64 let SubRegIndices = [sub_64];
67 // VSRL - One of the 32 128-bit VSX registers that overlap with the scalar
68 // floating-point registers.
69 class VSRL<FPR SubReg, string n> : PPCReg<n> {
70 let HWEncoding = SubReg.HWEncoding;
71 let SubRegs = [SubReg];
72 let SubRegIndices = [sub_64];
75 // VSRH - One of the 32 128-bit VSX registers that overlap with the vector
77 class VSRH<VR SubReg, string n> : PPCReg<n> {
78 let HWEncoding{4-0} = SubReg.HWEncoding{4-0};
79 let HWEncoding{5} = 1;
80 let SubRegs = [SubReg];
81 let SubRegIndices = [sub_128];
84 // CR - One of the 8 4-bit condition registers
85 class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
86 let HWEncoding{2-0} = num;
87 let SubRegs = subregs;
90 // CRBIT - One of the 32 1-bit condition register fields
91 class CRBIT<bits<5> num, string n> : PPCReg<n> {
92 let HWEncoding{4-0} = num;
95 // General-purpose registers
96 foreach Index = 0-31 in {
97 def R#Index : GPR<Index, "r"#Index>, DwarfRegNum<[-2, Index]>;
100 // 64-bit General-purpose registers
101 foreach Index = 0-31 in {
102 def X#Index : GP8<!cast<GPR>("R"#Index), "r"#Index>,
103 DwarfRegNum<[Index, -2]>;
106 // Floating-point registers
107 foreach Index = 0-31 in {
108 def F#Index : FPR<Index, "f"#Index>,
109 DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;
112 // Floating-point vector subregisters (for VSX)
113 foreach Index = 0-31 in {
114 def VF#Index : VF<Index, "vs" # !add(Index, 32)>;
118 foreach Index = 0-31 in {
119 def V#Index : VR<!cast<VF>("VF"#Index), "v"#Index>,
120 DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>;
124 foreach Index = 0-31 in {
125 def VSL#Index : VSRL<!cast<FPR>("F"#Index), "vs"#Index>,
126 DwarfRegAlias<!cast<FPR>("F"#Index)>;
128 foreach Index = 0-31 in {
129 def VSH#Index : VSRH<!cast<VR>("V"#Index), "vs" # !add(Index, 32)>,
130 DwarfRegAlias<!cast<VR>("V"#Index)>;
133 // The reprsentation of r0 when treated as the constant 0.
134 def ZERO : GPR<0, "0">;
135 def ZERO8 : GP8<ZERO, "0">;
137 // Representations of the frame pointer used by ISD::FRAMEADDR.
138 def FP : GPR<0 /* arbitrary */, "**FRAME POINTER**">;
139 def FP8 : GP8<FP, "**FRAME POINTER**">;
141 // Representations of the base pointer used by setjmp.
142 def BP : GPR<0 /* arbitrary */, "**BASE POINTER**">;
143 def BP8 : GP8<BP, "**BASE POINTER**">;
145 // Condition register bits
146 def CR0LT : CRBIT< 0, "0">;
147 def CR0GT : CRBIT< 1, "1">;
148 def CR0EQ : CRBIT< 2, "2">;
149 def CR0UN : CRBIT< 3, "3">;
150 def CR1LT : CRBIT< 4, "4">;
151 def CR1GT : CRBIT< 5, "5">;
152 def CR1EQ : CRBIT< 6, "6">;
153 def CR1UN : CRBIT< 7, "7">;
154 def CR2LT : CRBIT< 8, "8">;
155 def CR2GT : CRBIT< 9, "9">;
156 def CR2EQ : CRBIT<10, "10">;
157 def CR2UN : CRBIT<11, "11">;
158 def CR3LT : CRBIT<12, "12">;
159 def CR3GT : CRBIT<13, "13">;
160 def CR3EQ : CRBIT<14, "14">;
161 def CR3UN : CRBIT<15, "15">;
162 def CR4LT : CRBIT<16, "16">;
163 def CR4GT : CRBIT<17, "17">;
164 def CR4EQ : CRBIT<18, "18">;
165 def CR4UN : CRBIT<19, "19">;
166 def CR5LT : CRBIT<20, "20">;
167 def CR5GT : CRBIT<21, "21">;
168 def CR5EQ : CRBIT<22, "22">;
169 def CR5UN : CRBIT<23, "23">;
170 def CR6LT : CRBIT<24, "24">;
171 def CR6GT : CRBIT<25, "25">;
172 def CR6EQ : CRBIT<26, "26">;
173 def CR6UN : CRBIT<27, "27">;
174 def CR7LT : CRBIT<28, "28">;
175 def CR7GT : CRBIT<29, "29">;
176 def CR7EQ : CRBIT<30, "30">;
177 def CR7UN : CRBIT<31, "31">;
179 // Condition registers
180 let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in {
181 def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>;
182 def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>;
183 def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>;
184 def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>;
185 def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>;
186 def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>;
187 def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>;
188 def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>;
191 // The full condition-code register. This is not modeled fully, but defined
192 // here primarily, for compatibility with gcc, to allow the inline asm "cc"
193 // clobber specification to work.
194 def CC : PPCReg<"cc">, DwarfRegAlias<CR0> {
195 let Aliases = [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7];
199 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
200 //let Aliases = [LR] in
201 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
204 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
205 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
208 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
210 // Carry bit. In the architecture this is really bit 0 of the XER register
211 // (which really is SPR register 1); this is the only bit interesting to a
213 def CARRY: SPR<1, "ca">;
215 // FP rounding mode: bits 30 and 31 of the FP status and control register
216 // This is not allocated as a normal register; it appears only in
217 // Uses and Defs. The ABI says it needs to be preserved by a function,
218 // but this is not achieved by saving and restoring it as with
219 // most registers, it has to be done in code; to make this work all the
220 // return and call instructions are described as Uses of RM, so instructions
221 // that do nothing but change RM will not get deleted.
222 // Also, in the architecture it is not really a SPR; 512 is arbitrary.
223 def RM: SPR<512, "**ROUNDING MODE**">;
226 // Allocate volatiles first
227 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
228 def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12),
229 (sequence "R%u", 30, 13),
230 R31, R0, R1, FP, BP)>;
232 def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
233 (sequence "X%u", 30, 14),
234 X31, X13, X0, X1, FP8, BP8)>;
236 // For some instructions r0 is special (representing the value 0 instead of
237 // the value in the r0 register), and we use these register subclasses to
238 // prevent r0 from being allocated for use by those instructions.
239 def GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)>;
240 def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)>;
242 // Allocate volatiles first, then non-volatiles in reverse order. With the SVR4
243 // ABI the size of the Floating-point register save area is determined by the
244 // allocated non-volatile register with the lowest register number, as FP
245 // register N is spilled to offset 8 * (32 - N) below the back chain word of the
246 // previous stack frame. By allocating non-volatiles in reverse order we make
247 // sure that the Floating-point register save area is always as small as
248 // possible because there aren't any unused spill slots.
249 def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13),
250 (sequence "F%u", 31, 14))>;
251 def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
253 def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
254 (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
255 V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
256 V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>;
258 // VSX register classes (the allocation order mirrors that of the corresponding
259 // subregister classes).
260 def VSLRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
261 (add (sequence "VSL%u", 0, 13),
262 (sequence "VSL%u", 31, 14))>;
263 def VSHRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
264 (add VSH2, VSH3, VSH4, VSH5, VSH0, VSH1, VSH6, VSH7,
265 VSH8, VSH9, VSH10, VSH11, VSH12, VSH13, VSH14,
266 VSH15, VSH16, VSH17, VSH18, VSH19, VSH31, VSH30,
267 VSH29, VSH28, VSH27, VSH26, VSH25, VSH24, VSH23,
268 VSH22, VSH21, VSH20)>;
269 def VSRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
272 // Register classes for the 64-bit "scalar" VSX subregisters.
273 def VFRC : RegisterClass<"PPC", [f64], 64,
274 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7,
275 VF8, VF9, VF10, VF11, VF12, VF13, VF14,
276 VF15, VF16, VF17, VF18, VF19, VF31, VF30,
277 VF29, VF28, VF27, VF26, VF25, VF24, VF23,
279 def VSFRC : RegisterClass<"PPC", [f64], 64, (add F8RC, VFRC)>;
281 def CRBITRC : RegisterClass<"PPC", [i1], 32,
282 (add CR2LT, CR2GT, CR2EQ, CR2UN,
283 CR3LT, CR3GT, CR3EQ, CR3UN,
284 CR4LT, CR4GT, CR4EQ, CR4UN,
285 CR5LT, CR5GT, CR5EQ, CR5UN,
286 CR6LT, CR6GT, CR6EQ, CR6UN,
287 CR7LT, CR7GT, CR7EQ, CR7UN,
288 CR1LT, CR1GT, CR1EQ, CR1UN,
289 CR0LT, CR0GT, CR0EQ, CR0UN)> {
293 def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6,
294 CR7, CR2, CR3, CR4)>;
296 // The CTR registers are not allocatable because they're used by the
297 // decrement-and-branch instructions, and thus need to stay live across
298 // multiple basic blocks.
299 def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> {
300 let isAllocatable = 0;
302 def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> {
303 let isAllocatable = 0;
306 def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>;
307 def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> {
311 def CCRC : RegisterClass<"PPC", [i32], 32, (add CC)> {
312 let isAllocatable = 0;