1 //===-- PPCRegisterInfo.td - The PowerPC Register File -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 let Namespace = "PPC" in {
14 def sub_lt : SubRegIndex<1>;
15 def sub_gt : SubRegIndex<1, 1>;
16 def sub_eq : SubRegIndex<1, 2>;
17 def sub_un : SubRegIndex<1, 3>;
18 def sub_32 : SubRegIndex<32>;
22 class PPCReg<string n> : Register<n> {
23 let Namespace = "PPC";
26 // We identify all our registers with a 5-bit ID, for consistency's sake.
28 // GPR - One of the 32 32-bit general-purpose registers
29 class GPR<bits<5> num, string n> : PPCReg<n> {
30 let HWEncoding{4-0} = num;
33 // GP8 - One of the 32 64-bit general-purpose registers
34 class GP8<GPR SubReg, string n> : PPCReg<n> {
35 let HWEncoding = SubReg.HWEncoding;
36 let SubRegs = [SubReg];
37 let SubRegIndices = [sub_32];
40 // SPR - One of the 32-bit special-purpose registers
41 class SPR<bits<10> num, string n> : PPCReg<n> {
42 let HWEncoding{9-0} = num;
45 // FPR - One of the 32 64-bit floating-point registers
46 class FPR<bits<5> num, string n> : PPCReg<n> {
47 let HWEncoding{4-0} = num;
50 // VR - One of the 32 128-bit vector registers
51 class VR<bits<5> num, string n> : PPCReg<n> {
52 let HWEncoding{4-0} = num;
55 // CR - One of the 8 4-bit condition registers
56 class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
57 let HWEncoding{2-0} = num;
58 let SubRegs = subregs;
61 // CRBIT - One of the 32 1-bit condition register fields
62 class CRBIT<bits<5> num, string n> : PPCReg<n> {
63 let HWEncoding{4-0} = num;
66 // General-purpose registers
67 foreach Index = 0-31 in {
68 def R#Index : GPR<Index, "r"#Index>, DwarfRegNum<[-2, Index]>;
71 // 64-bit General-purpose registers
72 foreach Index = 0-31 in {
73 def X#Index : GP8<!cast<GPR>("R"#Index), "r"#Index>,
74 DwarfRegNum<[Index, -2]>;
77 // Floating-point registers
78 foreach Index = 0-31 in {
79 def F#Index : FPR<Index, "f"#Index>,
80 DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;
84 foreach Index = 0-31 in {
85 def V#Index : VR<Index, "v"#Index>,
86 DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>;
89 // The reprsentation of r0 when treated as the constant 0.
90 def ZERO : GPR<0, "0">;
91 def ZERO8 : GP8<ZERO, "0">;
93 // Representations of the frame pointer used by ISD::FRAMEADDR.
94 def FP : GPR<0 /* arbitrary */, "**FRAME POINTER**">;
95 def FP8 : GP8<FP, "**FRAME POINTER**">;
97 // Condition register bits
98 def CR0LT : CRBIT< 0, "0">;
99 def CR0GT : CRBIT< 1, "1">;
100 def CR0EQ : CRBIT< 2, "2">;
101 def CR0UN : CRBIT< 3, "3">;
102 def CR1LT : CRBIT< 4, "4">;
103 def CR1GT : CRBIT< 5, "5">;
104 def CR1EQ : CRBIT< 6, "6">;
105 def CR1UN : CRBIT< 7, "7">;
106 def CR2LT : CRBIT< 8, "8">;
107 def CR2GT : CRBIT< 9, "9">;
108 def CR2EQ : CRBIT<10, "10">;
109 def CR2UN : CRBIT<11, "11">;
110 def CR3LT : CRBIT<12, "12">;
111 def CR3GT : CRBIT<13, "13">;
112 def CR3EQ : CRBIT<14, "14">;
113 def CR3UN : CRBIT<15, "15">;
114 def CR4LT : CRBIT<16, "16">;
115 def CR4GT : CRBIT<17, "17">;
116 def CR4EQ : CRBIT<18, "18">;
117 def CR4UN : CRBIT<19, "19">;
118 def CR5LT : CRBIT<20, "20">;
119 def CR5GT : CRBIT<21, "21">;
120 def CR5EQ : CRBIT<22, "22">;
121 def CR5UN : CRBIT<23, "23">;
122 def CR6LT : CRBIT<24, "24">;
123 def CR6GT : CRBIT<25, "25">;
124 def CR6EQ : CRBIT<26, "26">;
125 def CR6UN : CRBIT<27, "27">;
126 def CR7LT : CRBIT<28, "28">;
127 def CR7GT : CRBIT<29, "29">;
128 def CR7EQ : CRBIT<30, "30">;
129 def CR7UN : CRBIT<31, "31">;
131 // Condition registers
132 let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in {
133 def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>;
134 def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>;
135 def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>;
136 def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>;
137 def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>;
138 def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>;
139 def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>;
140 def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>;
144 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
145 //let Aliases = [LR] in
146 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
149 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
150 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
153 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
155 // Carry bit. In the architecture this is really bit 0 of the XER register
156 // (which really is SPR register 1); this is the only bit interesting to a
158 def CARRY: SPR<1, "ca">;
160 // FP rounding mode: bits 30 and 31 of the FP status and control register
161 // This is not allocated as a normal register; it appears only in
162 // Uses and Defs. The ABI says it needs to be preserved by a function,
163 // but this is not achieved by saving and restoring it as with
164 // most registers, it has to be done in code; to make this work all the
165 // return and call instructions are described as Uses of RM, so instructions
166 // that do nothing but change RM will not get deleted.
167 // Also, in the architecture it is not really a SPR; 512 is arbitrary.
168 def RM: SPR<512, "**ROUNDING MODE**">;
171 // Allocate volatiles first
172 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
173 def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12),
174 (sequence "R%u", 30, 13),
177 def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
178 (sequence "X%u", 30, 14),
179 X31, X13, X0, X1, FP8)>;
181 // For some instructions r0 is special (representing the value 0 instead of
182 // the value in the r0 register), and we use these register subclasses to
183 // prevent r0 from being allocated for use by those instructions.
184 def GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)>;
185 def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)>;
187 // Allocate volatiles first, then non-volatiles in reverse order. With the SVR4
188 // ABI the size of the Floating-point register save area is determined by the
189 // allocated non-volatile register with the lowest register number, as FP
190 // register N is spilled to offset 8 * (32 - N) below the back chain word of the
191 // previous stack frame. By allocating non-volatiles in reverse order we make
192 // sure that the Floating-point register save area is always as small as
193 // possible because there aren't any unused spill slots.
194 def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13),
195 (sequence "F%u", 31, 14))>;
196 def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
198 def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
199 (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
200 V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
201 V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>;
203 def CRBITRC : RegisterClass<"PPC", [i32], 32,
204 (add CR0LT, CR0GT, CR0EQ, CR0UN,
205 CR1LT, CR1GT, CR1EQ, CR1UN,
206 CR2LT, CR2GT, CR2EQ, CR2UN,
207 CR3LT, CR3GT, CR3EQ, CR3UN,
208 CR4LT, CR4GT, CR4EQ, CR4UN,
209 CR5LT, CR5GT, CR5EQ, CR5UN,
210 CR6LT, CR6GT, CR6EQ, CR6UN,
211 CR7LT, CR7GT, CR7EQ, CR7UN)>
216 def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6,
217 CR7, CR2, CR3, CR4)>;
219 // The CTR registers are not allocatable because they're used by the
220 // decrement-and-branch instructions, and thus need to stay live across
221 // multiple basic blocks.
222 def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> {
223 let isAllocatable = 0;
225 def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> {
226 let isAllocatable = 0;
229 def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>;
230 def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> {