1 //===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
19 #include "llvm/ADT/DenseMap.h"
21 #define GET_REGINFO_HEADER
22 #include "PPCGenRegisterInfo.inc"
25 class PPCRegisterInfo : public PPCGenRegisterInfo {
26 DenseMap<unsigned, unsigned> ImmToIdxMap;
27 const PPCTargetMachine &TM;
29 PPCRegisterInfo(const PPCTargetMachine &TM);
31 /// getPointerRegClass - Return the register class to use to hold pointers.
32 /// This is used for addressing modes.
33 const TargetRegisterClass *
34 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
36 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
37 MachineFunction &MF) const override;
39 const TargetRegisterClass *
40 getLargestLegalSuperClass(const TargetRegisterClass *RC,
41 const MachineFunction &MF) const override;
43 /// Code Generation virtual methods...
44 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
45 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
46 CallingConv::ID CC) const override;
47 const uint32_t *getNoPreservedMask() const;
49 void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
51 BitVector getReservedRegs(const MachineFunction &MF) const override;
53 /// We require the register scavenger.
54 bool requiresRegisterScavenging(const MachineFunction &MF) const override {
58 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
62 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
66 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override {
70 void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
71 void lowerCRSpilling(MachineBasicBlock::iterator II,
72 unsigned FrameIndex) const;
73 void lowerCRRestore(MachineBasicBlock::iterator II,
74 unsigned FrameIndex) const;
75 void lowerCRBitSpilling(MachineBasicBlock::iterator II,
76 unsigned FrameIndex) const;
77 void lowerCRBitRestore(MachineBasicBlock::iterator II,
78 unsigned FrameIndex) const;
79 void lowerVRSAVESpilling(MachineBasicBlock::iterator II,
80 unsigned FrameIndex) const;
81 void lowerVRSAVERestore(MachineBasicBlock::iterator II,
82 unsigned FrameIndex) const;
84 bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
85 int &FrameIdx) const override;
86 void eliminateFrameIndex(MachineBasicBlock::iterator II,
87 int SPAdj, unsigned FIOperandNum,
88 RegScavenger *RS = nullptr) const override;
90 // Support for virtual base registers.
91 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
92 void materializeFrameBaseRegister(MachineBasicBlock *MBB,
93 unsigned BaseReg, int FrameIdx,
94 int64_t Offset) const override;
95 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
96 int64_t Offset) const override;
97 bool isFrameOffsetLegal(const MachineInstr *MI,
98 int64_t Offset) const override;
100 // Debug information queries.
101 unsigned getFrameRegister(const MachineFunction &MF) const override;
103 // Base pointer (stack realignment) support.
104 unsigned getBaseRegister(const MachineFunction &MF) const;
105 bool hasBasePointer(const MachineFunction &MF) const;
106 bool canRealignStack(const MachineFunction &MF) const;
107 bool needsStackRealignment(const MachineFunction &MF) const override;
110 } // end namespace llvm