1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PPCInstrBuilder.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCRegisterInfo.h"
19 #include "PPCFrameInfo.h"
20 #include "PPCSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Type.h"
23 #include "llvm/CodeGen/ValueTypes.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/Target/TargetFrameInfo.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
42 /// getRegisterNumbering - Given the enum value for some register, e.g.
43 /// PPC::F14, return the number that it corresponds to (e.g. 14).
44 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
47 case R0 : case X0 : case F0 : case V0 : case CR0: return 0;
48 case R1 : case X1 : case F1 : case V1 : case CR1: return 1;
49 case R2 : case X2 : case F2 : case V2 : case CR2: return 2;
50 case R3 : case X3 : case F3 : case V3 : case CR3: return 3;
51 case R4 : case X4 : case F4 : case V4 : case CR4: return 4;
52 case R5 : case X5 : case F5 : case V5 : case CR5: return 5;
53 case R6 : case X6 : case F6 : case V6 : case CR6: return 6;
54 case R7 : case X7 : case F7 : case V7 : case CR7: return 7;
55 case R8 : case X8 : case F8 : case V8 : return 8;
56 case R9 : case X9 : case F9 : case V9 : return 9;
57 case R10: case X10: case F10: case V10: return 10;
58 case R11: case X11: case F11: case V11: return 11;
59 case R12: case X12: case F12: case V12: return 12;
60 case R13: case X13: case F13: case V13: return 13;
61 case R14: case X14: case F14: case V14: return 14;
62 case R15: case X15: case F15: case V15: return 15;
63 case R16: case X16: case F16: case V16: return 16;
64 case R17: case X17: case F17: case V17: return 17;
65 case R18: case X18: case F18: case V18: return 18;
66 case R19: case X19: case F19: case V19: return 19;
67 case R20: case X20: case F20: case V20: return 20;
68 case R21: case X21: case F21: case V21: return 21;
69 case R22: case X22: case F22: case V22: return 22;
70 case R23: case X23: case F23: case V23: return 23;
71 case R24: case X24: case F24: case V24: return 24;
72 case R25: case X25: case F25: case V25: return 25;
73 case R26: case X26: case F26: case V26: return 26;
74 case R27: case X27: case F27: case V27: return 27;
75 case R28: case X28: case F28: case V28: return 28;
76 case R29: case X29: case F29: case V29: return 29;
77 case R30: case X30: case F30: case V30: return 30;
78 case R31: case X31: case F31: case V31: return 31;
80 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
85 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
86 const TargetInstrInfo &tii)
87 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
88 Subtarget(ST), TII(tii) {
89 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
90 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
91 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
92 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
93 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
94 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
95 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
96 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
97 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
101 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
102 MachineBasicBlock::iterator MI,
103 unsigned SrcReg, int FrameIdx,
104 const TargetRegisterClass *RC) const {
105 if (RC == PPC::GPRCRegisterClass) {
106 if (SrcReg != PPC::LR) {
107 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
108 .addReg(SrcReg, false, false, true), FrameIdx);
110 // FIXME: this spills LR immediately to memory in one step. To do this,
111 // we use R11, which we know cannot be used in the prolog/epilog. This is
113 BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11);
114 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
115 .addReg(PPC::R11, false, false, true), FrameIdx);
117 } else if (RC == PPC::G8RCRegisterClass) {
118 if (SrcReg != PPC::LR8) {
119 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD))
120 .addReg(SrcReg, false, false, true), FrameIdx);
122 // FIXME: this spills LR immediately to memory in one step. To do this,
123 // we use R11, which we know cannot be used in the prolog/epilog. This is
125 BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11);
126 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD))
127 .addReg(PPC::X11, false, false, true), FrameIdx);
129 } else if (RC == PPC::F8RCRegisterClass) {
130 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD))
131 .addReg(SrcReg, false, false, true), FrameIdx);
132 } else if (RC == PPC::F4RCRegisterClass) {
133 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS))
134 .addReg(SrcReg, false, false, true), FrameIdx);
135 } else if (RC == PPC::CRRCRegisterClass) {
136 // FIXME: We use R0 here, because it isn't available for RA.
137 // We need to store the CR in the low 4-bits of the saved value. First,
138 // issue a MFCR to save all of the CRBits.
139 BuildMI(MBB, MI, TII.get(PPC::MFCR), PPC::R0);
141 // If the saved register wasn't CR0, shift the bits left so that they are in
143 if (SrcReg != PPC::CR0) {
144 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
145 // rlwinm r0, r0, ShiftBits, 0, 31.
146 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0)
147 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31);
150 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
151 .addReg(PPC::R0, false, false, true), FrameIdx);
152 } else if (RC == PPC::VRRCRegisterClass) {
153 // We don't have indexed addressing for vector loads. Emit:
155 // Dest = LVX R0, R11
157 // FIXME: We use R0 here, because it isn't available for RA.
158 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
160 BuildMI(MBB, MI, TII.get(PPC::STVX))
161 .addReg(SrcReg, false, false, true).addReg(PPC::R0).addReg(PPC::R0);
163 assert(0 && "Unknown regclass!");
169 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
170 MachineBasicBlock::iterator MI,
171 unsigned DestReg, int FrameIdx,
172 const TargetRegisterClass *RC) const {
173 if (RC == PPC::GPRCRegisterClass) {
174 if (DestReg != PPC::LR) {
175 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), DestReg), FrameIdx);
177 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R11),FrameIdx);
178 BuildMI(MBB, MI, TII.get(PPC::MTLR)).addReg(PPC::R11);
180 } else if (RC == PPC::G8RCRegisterClass) {
181 if (DestReg != PPC::LR8) {
182 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), DestReg), FrameIdx);
184 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), PPC::R11), FrameIdx);
185 BuildMI(MBB, MI, TII.get(PPC::MTLR8)).addReg(PPC::R11);
187 } else if (RC == PPC::F8RCRegisterClass) {
188 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFD), DestReg), FrameIdx);
189 } else if (RC == PPC::F4RCRegisterClass) {
190 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFS), DestReg), FrameIdx);
191 } else if (RC == PPC::CRRCRegisterClass) {
192 // FIXME: We use R0 here, because it isn't available for RA.
193 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R0), FrameIdx);
195 // If the reloaded register isn't CR0, shift the bits right so that they are
196 // in the right CR's slot.
197 if (DestReg != PPC::CR0) {
198 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
199 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
200 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0)
201 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31);
204 BuildMI(MBB, MI, TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0);
205 } else if (RC == PPC::VRRCRegisterClass) {
206 // We don't have indexed addressing for vector loads. Emit:
208 // Dest = LVX R0, R11
210 // FIXME: We use R0 here, because it isn't available for RA.
211 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
213 BuildMI(MBB, MI, TII.get(PPC::LVX),DestReg).addReg(PPC::R0).addReg(PPC::R0);
215 assert(0 && "Unknown regclass!");
220 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
221 MachineBasicBlock::iterator MI,
222 unsigned DestReg, unsigned SrcReg,
223 const TargetRegisterClass *RC) const {
224 if (RC == PPC::GPRCRegisterClass) {
225 BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
226 } else if (RC == PPC::G8RCRegisterClass) {
227 BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
228 } else if (RC == PPC::F4RCRegisterClass) {
229 BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg);
230 } else if (RC == PPC::F8RCRegisterClass) {
231 BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg);
232 } else if (RC == PPC::CRRCRegisterClass) {
233 BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg);
234 } else if (RC == PPC::VRRCRegisterClass) {
235 BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
237 cerr << "Attempt to copy register that is not GPR or FPR";
242 void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
243 MachineBasicBlock::iterator I,
245 const MachineInstr *Orig) const {
246 MachineInstr *MI = Orig->clone();
247 MI->getOperand(0).setReg(DestReg);
251 const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const {
252 // 32-bit Darwin calling convention.
253 static const unsigned Darwin32_CalleeSavedRegs[] = {
254 PPC::R13, PPC::R14, PPC::R15,
255 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
256 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
257 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
258 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
260 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
261 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
262 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
263 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
266 PPC::CR2, PPC::CR3, PPC::CR4,
267 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
268 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
269 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
274 static const unsigned ELF32_CalleeSavedRegs[] = {
275 PPC::R13, PPC::R14, PPC::R15,
276 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
277 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
278 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
279 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
282 PPC::F10, PPC::F11, PPC::F12, PPC::F13,
283 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
284 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
285 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
286 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
289 PPC::CR2, PPC::CR3, PPC::CR4,
290 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
291 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
292 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
296 // 64-bit Darwin calling convention.
297 static const unsigned Darwin64_CalleeSavedRegs[] = {
299 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
300 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
301 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
302 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
304 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
305 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
306 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
307 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
310 PPC::CR2, PPC::CR3, PPC::CR4,
311 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
312 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
313 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
318 static const unsigned ELF64_CalleeSavedRegs[] = {
320 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
321 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
322 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
323 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
326 PPC::F10, PPC::F11, PPC::F12, PPC::F13,
327 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
328 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
329 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
330 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
333 PPC::CR2, PPC::CR3, PPC::CR4,
334 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
335 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
336 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
341 if (Subtarget.isMachoABI())
342 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
343 Darwin32_CalleeSavedRegs;
346 return Subtarget.isPPC64() ? ELF64_CalleeSavedRegs : ELF32_CalleeSavedRegs;
349 const TargetRegisterClass* const*
350 PPCRegisterInfo::getCalleeSavedRegClasses() const {
351 // 32-bit Darwin calling convention.
352 static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = {
353 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
354 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
355 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
356 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
357 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
359 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
360 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
361 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
362 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
363 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
365 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
367 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
368 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
369 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
371 &PPC::GPRCRegClass, 0
374 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = {
375 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
376 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
377 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
378 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
379 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
382 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
383 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
384 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
385 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
386 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
387 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
389 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
391 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
392 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
393 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
395 &PPC::GPRCRegClass, 0
398 // 64-bit Darwin calling convention.
399 static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = {
400 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
401 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
402 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
403 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
404 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
406 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
407 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
408 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
409 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
410 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
412 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
414 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
415 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
416 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
418 &PPC::G8RCRegClass, 0
421 static const TargetRegisterClass * const ELF64_CalleeSavedRegClasses[] = {
422 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
423 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
424 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
425 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
426 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
429 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
430 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
431 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
432 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
433 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
434 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
436 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
438 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
439 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
440 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
442 &PPC::G8RCRegClass, 0
445 if (Subtarget.isMachoABI())
446 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses :
447 Darwin32_CalleeSavedRegClasses;
450 return Subtarget.isPPC64() ? ELF64_CalleeSavedRegClasses :
451 ELF32_CalleeSavedRegClasses;
454 // needsFP - Return true if the specified function should have a dedicated frame
455 // pointer register. This is true if the function has variable sized allocas or
456 // if frame pointer elimination is disabled.
458 static bool needsFP(const MachineFunction &MF) {
459 const MachineFrameInfo *MFI = MF.getFrameInfo();
460 return NoFramePointerElim || MFI->hasVarSizedObjects();
463 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
464 BitVector Reserved(getNumRegs());
465 Reserved.set(PPC::R0);
466 Reserved.set(PPC::R1);
467 Reserved.set(PPC::LR);
468 // In Linux, r2 is reserved for the OS.
469 if (!Subtarget.isDarwin())
470 Reserved.set(PPC::R2);
471 // On PPC64, r13 is the thread pointer. Never allocate this register.
472 // Note that this is overconservative, as it also prevents allocation of
473 // R31 when the FP is not needed.
474 if (Subtarget.isPPC64()) {
475 Reserved.set(PPC::R13);
476 Reserved.set(PPC::R31);
479 Reserved.set(PPC::R31);
483 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
484 /// copy instructions, turning them into load/store instructions.
485 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
487 int FrameIndex) const {
488 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
489 // it takes more than one instruction to store it.
490 unsigned Opc = MI->getOpcode();
492 MachineInstr *NewMI = NULL;
493 if ((Opc == PPC::OR &&
494 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
495 if (OpNum == 0) { // move -> store
496 unsigned InReg = MI->getOperand(1).getReg();
497 NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg),
499 } else { // move -> load
500 unsigned OutReg = MI->getOperand(0).getReg();
501 NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg),
504 } else if ((Opc == PPC::OR8 &&
505 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
506 if (OpNum == 0) { // move -> store
507 unsigned InReg = MI->getOperand(1).getReg();
508 NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg),
510 } else { // move -> load
511 unsigned OutReg = MI->getOperand(0).getReg();
512 NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex);
514 } else if (Opc == PPC::FMRD) {
515 if (OpNum == 0) { // move -> store
516 unsigned InReg = MI->getOperand(1).getReg();
517 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg),
519 } else { // move -> load
520 unsigned OutReg = MI->getOperand(0).getReg();
521 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex);
523 } else if (Opc == PPC::FMRS) {
524 if (OpNum == 0) { // move -> store
525 unsigned InReg = MI->getOperand(1).getReg();
526 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg),
528 } else { // move -> load
529 unsigned OutReg = MI->getOperand(0).getReg();
530 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex);
535 NewMI->copyKillDeadInfo(MI);
539 //===----------------------------------------------------------------------===//
540 // Stack Frame Processing methods
541 //===----------------------------------------------------------------------===//
543 // hasFP - Return true if the specified function actually has a dedicated frame
544 // pointer register. This is true if the function needs a frame pointer and has
545 // a non-zero stack size.
546 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
547 const MachineFrameInfo *MFI = MF.getFrameInfo();
548 return MFI->getStackSize() && needsFP(MF);
551 /// usesLR - Returns if the link registers (LR) has been used in the function.
553 bool PPCRegisterInfo::usesLR(MachineFunction &MF) const {
554 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
558 void PPCRegisterInfo::
559 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
560 MachineBasicBlock::iterator I) const {
561 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
565 /// LowerDynamicAlloc - Generate the code for allocating an object in the
566 /// current frame. The sequence of code with be in the general form
568 /// addi R0, SP, #frameSize ; get the address of the previous frame
569 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
570 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation
572 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
573 // Get the instruction.
574 MachineInstr &MI = *II;
575 // Get the instruction's basic block.
576 MachineBasicBlock &MBB = *MI.getParent();
577 // Get the basic block's function.
578 MachineFunction &MF = *MBB.getParent();
579 // Get the frame info.
580 MachineFrameInfo *MFI = MF.getFrameInfo();
581 // Determine whether 64-bit pointers are used.
582 bool LP64 = Subtarget.isPPC64();
584 // Get the maximum call stack size.
585 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
586 // Get the total frame size.
587 unsigned FrameSize = MFI->getStackSize();
589 // Get stack alignments.
590 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
591 unsigned MaxAlign = MFI->getMaxAlignment();
592 assert(MaxAlign <= TargetAlign &&
593 "Dynamic alloca with large aligns not supported");
595 // Determine the previous frame's address. If FrameSize can't be
596 // represented as 16 bits or we need special alignment, then we load the
597 // previous frame's address from 0(SP). Why not do an addis of the hi?
598 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
599 // Constructing the constant and adding would take 3 instructions.
600 // Fortunately, a frame greater than 32K is rare.
601 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
602 BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0)
606 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
610 BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0)
615 // Grow the stack and update the stack pointer link, then
616 // determine the address of new allocated space.
618 BuildMI(MBB, II, TII.get(PPC::STDUX))
621 .addReg(MI.getOperand(1).getReg());
622 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
624 .addImm(maxCallFrameSize);
626 BuildMI(MBB, II, TII.get(PPC::STWUX))
629 .addReg(MI.getOperand(1).getReg());
630 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
632 .addImm(maxCallFrameSize);
635 // Discard the DYNALLOC instruction.
639 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
640 RegScavenger *RS) const {
641 // Get the instruction.
642 MachineInstr &MI = *II;
643 // Get the instruction's basic block.
644 MachineBasicBlock &MBB = *MI.getParent();
645 // Get the basic block's function.
646 MachineFunction &MF = *MBB.getParent();
647 // Get the frame info.
648 MachineFrameInfo *MFI = MF.getFrameInfo();
650 // Find out which operand is the frame index.
652 while (!MI.getOperand(i).isFrameIndex()) {
654 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
656 // Take into account whether it's an add or mem instruction
657 unsigned OffIdx = (i == 2) ? 1 : 2;
658 if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
661 // Get the frame index.
662 int FrameIndex = MI.getOperand(i).getFrameIndex();
664 // Get the frame pointer save index. Users of this index are primarily
665 // DYNALLOC instructions.
666 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
667 int FPSI = FI->getFramePointerSaveIndex();
668 // Get the instruction opcode.
669 unsigned OpC = MI.getOpcode();
671 // Special case for dynamic alloca.
672 if (FPSI && FrameIndex == FPSI &&
673 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
674 lowerDynamicAlloc(II);
678 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
679 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false);
681 // Figure out if the offset in the instruction is shifted right two bits. This
682 // is true for instructions like "STD", which the machine implicitly adds two
684 bool isIXAddr = false;
694 // Now add the frame object offset to the offset from r1.
695 int Offset = MFI->getObjectOffset(FrameIndex);
698 Offset += MI.getOperand(OffIdx).getImmedValue();
700 Offset += MI.getOperand(OffIdx).getImmedValue() << 2;
702 // If we're not using a Frame Pointer that has been set to the value of the
703 // SP before having the stack size subtracted from it, then add the stack size
704 // to Offset to get the correct offset.
705 Offset += MFI->getStackSize();
707 if (!isInt16(Offset)) {
708 // Insert a set of r0 with the full offset value before the ld, st, or add
709 BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16);
710 BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset);
712 // convert into indexed form of the instruction
713 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
714 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
715 assert(ImmToIdxMap.count(OpC) &&
716 "No indexed form of load or store available!");
717 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
718 MI.setInstrDescriptor(TII.get(NewOpcode));
719 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false);
720 MI.getOperand(2).ChangeToRegister(PPC::R0, false);
723 assert((Offset & 3) == 0 && "Invalid frame offset!");
724 Offset >>= 2; // The actual encoded value has the low two bits zero.
726 MI.getOperand(OffIdx).ChangeToImmediate(Offset);
730 /// VRRegNo - Map from a numbered VR register to its enum value.
732 static const unsigned short VRRegNo[] = {
733 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
734 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
735 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
736 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
739 /// RemoveVRSaveCode - We have found that this function does not need any code
740 /// to manipulate the VRSAVE register, even though it uses vector registers.
741 /// This can happen when the only registers used are known to be live in or out
742 /// of the function. Remove all of the VRSAVE related code from the function.
743 static void RemoveVRSaveCode(MachineInstr *MI) {
744 MachineBasicBlock *Entry = MI->getParent();
745 MachineFunction *MF = Entry->getParent();
747 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
748 MachineBasicBlock::iterator MBBI = MI;
750 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
751 MBBI->eraseFromParent();
753 bool RemovedAllMTVRSAVEs = true;
754 // See if we can find and remove the MTVRSAVE instruction from all of the
756 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
757 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
758 // If last instruction is a return instruction, add an epilogue
759 if (!I->empty() && TII.isReturn(I->back().getOpcode())) {
760 bool FoundIt = false;
761 for (MBBI = I->end(); MBBI != I->begin(); ) {
763 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
764 MBBI->eraseFromParent(); // remove it.
769 RemovedAllMTVRSAVEs &= FoundIt;
773 // If we found and removed all MTVRSAVE instructions, remove the read of
775 if (RemovedAllMTVRSAVEs) {
777 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
779 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
780 MBBI->eraseFromParent();
783 // Finally, nuke the UPDATE_VRSAVE.
784 MI->eraseFromParent();
787 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
788 // instruction selector. Based on the vector registers that have been used,
789 // transform this into the appropriate ORI instruction.
790 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs,
791 const TargetInstrInfo &TII) {
792 unsigned UsedRegMask = 0;
793 for (unsigned i = 0; i != 32; ++i)
794 if (UsedRegs[VRRegNo[i]])
795 UsedRegMask |= 1 << (31-i);
797 // Live in and live out values already must be in the mask, so don't bother
799 MachineFunction *MF = MI->getParent()->getParent();
800 for (MachineFunction::livein_iterator I =
801 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) {
802 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
803 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
804 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
806 for (MachineFunction::liveout_iterator I =
807 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) {
808 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
809 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
810 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
813 unsigned SrcReg = MI->getOperand(1).getReg();
814 unsigned DstReg = MI->getOperand(0).getReg();
815 // If no registers are used, turn this into a copy.
816 if (UsedRegMask == 0) {
817 // Remove all VRSAVE code.
818 RemoveVRSaveCode(MI);
820 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
821 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
822 .addReg(SrcReg).addImm(UsedRegMask);
823 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
824 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
825 .addReg(SrcReg).addImm(UsedRegMask >> 16);
827 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
828 .addReg(SrcReg).addImm(UsedRegMask >> 16);
829 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
830 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
833 // Remove the old UPDATE_VRSAVE instruction.
834 MI->eraseFromParent();
837 /// determineFrameLayout - Determine the size of the frame and maximum call
839 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
840 MachineFrameInfo *MFI = MF.getFrameInfo();
842 // Get the number of bytes to allocate from the FrameInfo
843 unsigned FrameSize = MFI->getStackSize();
845 // Get the alignments provided by the target, and the maximum alignment
846 // (if any) of the fixed frame objects.
847 unsigned MaxAlign = MFI->getMaxAlignment();
848 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
849 unsigned AlignMask = TargetAlign - 1; //
851 // If we are a leaf function, and use up to 224 bytes of stack space,
852 // don't have a frame pointer, calls, or dynamic alloca then we do not need
853 // to adjust the stack pointer (we fit in the Red Zone).
854 if (FrameSize <= 224 && // Fits in red zone.
855 !MFI->hasVarSizedObjects() && // No dynamic alloca.
856 !MFI->hasCalls() && // No calls.
857 MaxAlign <= TargetAlign) { // No special alignment.
859 MFI->setStackSize(0);
863 // Get the maximum call frame size of all the calls.
864 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
866 // Maximum call frame needs to be at least big enough for linkage and 8 args.
867 unsigned minCallFrameSize =
868 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
869 Subtarget.isMachoABI());
870 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
872 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
873 // that allocations will be aligned.
874 if (MFI->hasVarSizedObjects())
875 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
877 // Update maximum call frame size.
878 MFI->setMaxCallFrameSize(maxCallFrameSize);
880 // Include call frame size in total.
881 FrameSize += maxCallFrameSize;
883 // Make sure the frame is aligned.
884 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
886 // Update frame info.
887 MFI->setStackSize(FrameSize);
890 void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
893 // Save and clear the LR state.
894 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
895 unsigned LR = getRARegister();
896 FI->setUsesLR(MF.isPhysRegUsed(LR));
897 MF.changePhyRegUsed(LR, false);
900 // Save R31 if necessary
901 int FPSI = FI->getFramePointerSaveIndex();
902 bool IsPPC64 = Subtarget.isPPC64();
903 bool IsELF_ABI = Subtarget.isELF_ABI();
904 const MachineFrameInfo *MFI = MF.getFrameInfo();
906 // If the frame pointer save index hasn't been defined yet.
907 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects())
909 // Find out what the fix offset of the frame pointer save area.
910 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
912 // Allocate the frame index for frame pointer save area.
913 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
915 FI->setFramePointerSaveIndex(FPSI);
920 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
921 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
922 MachineBasicBlock::iterator MBBI = MBB.begin();
923 MachineFrameInfo *MFI = MF.getFrameInfo();
924 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
926 // Prepare for frame info.
927 unsigned FrameLabelId = 0;
929 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
931 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
932 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
933 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs(), TII);
938 // Move MBBI back to the beginning of the function.
941 // Work out frame sizes.
942 determineFrameLayout(MF);
943 unsigned FrameSize = MFI->getStackSize();
945 int NegFrameSize = -FrameSize;
947 // Get processor type.
948 bool IsPPC64 = Subtarget.isPPC64();
949 // Get operating system
950 bool IsMachoABI = Subtarget.isMachoABI();
951 // Check if the link register (LR) has been used.
952 bool UsesLR = MFI->hasCalls() || usesLR(MF);
953 // Do we have a frame pointer for this function?
954 bool HasFP = hasFP(MF) && FrameSize;
956 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
957 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
961 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0);
964 BuildMI(MBB, MBBI, TII.get(PPC::STD))
965 .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1);
968 BuildMI(MBB, MBBI, TII.get(PPC::STD))
969 .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1);
972 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0);
975 BuildMI(MBB, MBBI, TII.get(PPC::STW))
976 .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1);
979 BuildMI(MBB, MBBI, TII.get(PPC::STW))
980 .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1);
983 // Skip if a leaf routine.
984 if (!FrameSize) return;
986 // Get stack alignments.
987 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
988 unsigned MaxAlign = MFI->getMaxAlignment();
990 if (MMI && MMI->needsFrameInfo()) {
991 // Mark effective beginning of when frame pointer becomes valid.
992 FrameLabelId = MMI->NextLabelID();
993 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId);
996 // Adjust stack pointer: r1 += NegFrameSize.
997 // If there is a preferred stack alignment, align R1 now
1000 if (MaxAlign > TargetAlign) {
1001 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1002 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1003 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
1004 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
1005 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0)
1006 .addImm(NegFrameSize);
1007 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
1008 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
1009 } else if (isInt16(NegFrameSize)) {
1010 BuildMI(MBB, MBBI, TII.get(PPC::STWU),
1011 PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1);
1013 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16);
1014 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0)
1015 .addImm(NegFrameSize & 0xFFFF);
1016 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1)
1020 if (MaxAlign > TargetAlign) {
1021 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1022 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1023 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
1024 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign));
1025 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0)
1026 .addImm(NegFrameSize);
1027 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
1028 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0);
1029 } else if (isInt16(NegFrameSize)) {
1030 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
1031 .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1);
1033 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16);
1034 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0)
1035 .addImm(NegFrameSize & 0xFFFF);
1036 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1)
1041 if (MMI && MMI->needsFrameInfo()) {
1042 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1045 // Show update of SP.
1046 MachineLocation SPDst(MachineLocation::VirtualFP);
1047 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
1048 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1050 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
1051 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
1055 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
1056 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
1057 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
1060 // Add callee saved registers to move list.
1061 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1062 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1063 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1064 unsigned Reg = CSI[I].getReg();
1065 if (Reg == PPC::LR || Reg == PPC::LR8) continue;
1066 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1067 MachineLocation CSSrc(Reg);
1068 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1071 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
1072 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
1073 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
1075 // Mark effective beginning of when frame pointer is ready.
1076 unsigned ReadyLabelId = MMI->NextLabelID();
1077 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId);
1079 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
1080 (IsPPC64 ? PPC::X1 : PPC::R1));
1081 MachineLocation FPSrc(MachineLocation::VirtualFP);
1082 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1085 // If there is a frame pointer, copy R1 into R31
1088 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1)
1091 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1)
1097 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
1098 MachineBasicBlock &MBB) const {
1099 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1100 assert(MBBI->getOpcode() == PPC::BLR &&
1101 "Can only insert epilog into returning blocks");
1103 // Get alignment info so we know how to restore r1
1104 const MachineFrameInfo *MFI = MF.getFrameInfo();
1105 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1106 unsigned MaxAlign = MFI->getMaxAlignment();
1108 // Get the number of bytes allocated from the FrameInfo.
1109 unsigned FrameSize = MFI->getStackSize();
1111 // Get processor type.
1112 bool IsPPC64 = Subtarget.isPPC64();
1113 // Get operating system
1114 bool IsMachoABI = Subtarget.isMachoABI();
1115 // Check if the link register (LR) has been used.
1116 bool UsesLR = MFI->hasCalls() || usesLR(MF);
1117 // Do we have a frame pointer for this function?
1118 bool HasFP = hasFP(MF) && FrameSize;
1120 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
1121 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
1124 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
1125 // on entry to the function. Add this offset back now.
1126 if (!Subtarget.isPPC64()) {
1127 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1128 !MFI->hasVarSizedObjects()) {
1129 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
1130 .addReg(PPC::R1).addImm(FrameSize);
1132 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
1135 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1136 !MFI->hasVarSizedObjects()) {
1137 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
1138 .addReg(PPC::X1).addImm(FrameSize);
1140 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
1147 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0)
1148 .addImm(LROffset/4).addReg(PPC::X1);
1151 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
1152 .addImm(FPOffset/4).addReg(PPC::X1);
1155 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0);
1158 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0)
1159 .addImm(LROffset).addReg(PPC::R1);
1162 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
1163 .addImm(FPOffset).addReg(PPC::R1);
1166 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0);
1170 unsigned PPCRegisterInfo::getRARegister() const {
1171 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
1174 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1175 if (!Subtarget.isPPC64())
1176 return hasFP(MF) ? PPC::R31 : PPC::R1;
1178 return hasFP(MF) ? PPC::X31 : PPC::X1;
1181 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1183 // Initial state of the frame pointer is R1.
1184 MachineLocation Dst(MachineLocation::VirtualFP);
1185 MachineLocation Src(PPC::R1, 0);
1186 Moves.push_back(MachineMove(0, Dst, Src));
1189 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
1190 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
1193 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
1194 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
1197 #include "PPCGenRegisterInfo.inc"